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EP1050905

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EP About this file: EP1050905

EP1050905 - Method of producing a semiconductor device with insulating layer [Right-click to bookmark this link]
Former [2000/45]	Semiconductor device with insulating layer
	[2016/51]
Status	No opposition filed within time limit Status updated on 27.04.2018 Database last updated on 03.10.2024
Former	The patent has been granted Status updated on 19.05.2017
Former	Grant of patent is intended Status updated on 07.12.2016
Most recent event Tooltip	27.04.2018	No opposition filed within time limit	published on 30.05.2018 [2018/22]
Applicant(s)	For all designated states SHINKO ELECTRIC INDUSTRIES CO. LTD. 80, Oshimada-machi Nagano-shi Nagano 381-2287 / JP
	[2017/21]
Former [2000/45]	For all designated states SHINKO ELECTRIC INDUSTRIES CO. LTD. 711, Aza Shariden, Oaza Kurita Nagano-shi, Nagano 380-0921 / JP
Inventor(s)	01 / Ito, Daisuke, @Shinko Electric Industries Co., Ltd. 80, Oshimada-machi Nagano-shi, Nagano 381-2287 / JP
	02 / Kitahara, Yuichi, @Shinko Electric Industries Co., Ltd. 80, Oshimada-machi Nagano-shi, Nagano 381-2287 / JP
	[2017/20]
Former [2000/45]	01 / Ito, Daisuke, Shinko Electric Industrie Co., Ltd. 711 Aza Shariden, Oaza Kurita Nagano-shi, Nagano 380-0921 / JP
	02 / Kitahara, Yuichi, Sh Electric Industrie Co., Ltd. 711 Aza Shariden, Oaza Kurita Nagano-shi, Nagano 380-0921 / JP
Representative(s)	Gill Jennings & Every LLP The Broadgate Tower 20 Primrose Street London EC2A 2ES / GB
	[2017/25]
Former [2005/45]	Finnie, Peter John, et al Gill Jennings & Every, Broadgate House, 7 Eldon Street London EC2M 7LH / GB
Former [2000/45]	Rackham, Stephen Neil GILL JENNINGS & EVERY, Broadgate House, 7 Eldon Street London EC2M 7LH / GB
Application number, filing date	00303721.5	03.05.2000
	[2000/45]
Priority number, date	JP19990127120	07.05.1999 Original published format: JP 12712099
	[2000/45]
Filing language	EN
Procedural language	EN
Publication	Type:	A2 Application without search report
	No.:	EP1050905
	Date:	08.11.2000
	Language:	EN
	[2000/45]
	Type:	A3 Search report
	No.:	EP1050905
	Date:	12.09.2001
	[2001/37]
	Type:	B1 Patent specification
	No.:	EP1050905
	Date:	21.06.2017
	Language:	EN
	[2017/25]
Search report(s)	(Supplementary) European search report - dispatched on:	EP	01.08.2001
Classification	IPC:	H01L23/31, H01L21/768, H01L21/60	[2016/51]
	CPC:	H01L24/12 (EP,US); H01L21/76814 (EP,KR,US); H01L21/32135 (KR); H01L21/32139 (KR); H01L21/76883 (KR); H01L23/3114 (EP,KR,US); (+) H01L24/03 (EP,US); H01L24/05 (EP,US); H01L24/11 (EP,KR,US); H01L2224/0231 (EP,US); H01L2224/0401 (EP,US); H01L2224/04042 (EP,US); H01L2224/05624 (EP,US); H01L2224/05647 (EP,US); H01L2224/11334 (EP,US); H01L2224/1147 (EP,US); H01L2224/13099 (EP,US); H01L2224/45144 (EP,US); H01L2224/48624 (EP,US); H01L2224/48647 (EP,US); H01L24/45 (EP,US); H01L2924/01006 (EP,US); H01L2924/01007 (EP,US); H01L2924/01011 (EP,US); H01L2924/01013 (EP,US); H01L2924/01014 (EP,US); H01L2924/01018 (EP,US); H01L2924/01024 (EP,US); H01L2924/01027 (EP,US); H01L2924/01028 (EP,US); H01L2924/01029 (EP,US); H01L2924/01033 (EP,US); H01L2924/01075 (EP,US); H01L2924/01078 (EP,US); H01L2924/01079 (EP,US); H01L2924/014 (EP,US); H01L2924/05042 (EP,US); H01L2924/12042 (EP,US) (-)
	C-Set:	H01L2224/04042, H01L2924/00 (EP,US); H01L2224/05624, H01L2924/00014 (US,EP); H01L2224/45144, H01L2924/00014 (EP,US); H01L2224/48624, H01L2924/00 (US,EP); (+) H01L2224/48647, H01L2924/00 (US,EP); H01L2924/12042, H01L2924/00 (EP,US) (-)
	Former IPC [2001/37]	H01L21/768, H01L21/60
	Former IPC [2000/45]	H01L21/768
Designated contracting states	DE, FR [2017/25]
Former [2002/23]	DE, FR
Former [2000/45]	AT, BE, CH, CY, DE, DK, ES, FI, FR, GB, GR, IE, IT, LI, LU, MC, NL, PT, SE
Title	German:	Verfahren zur Herstellung einer Halbleitervorrichtung mit isolierender Schicht	[2016/51]
	English:	Method of producing a semiconductor device with insulating layer	[2016/51]
	French:	Procédé de fabrication d'un dispositif semiconducteur avec couche isolante	[2016/51]
	Former [2000/45]	Halbleitervorrichtung mit isolierender Schicht
	Former [2000/45]	Semiconductor device with insulating layer
	Former [2000/45]	Dispositif semiconducteur avec couche isolante
Examination procedure	15.02.2002	Examination requested [2002/17]
	18.01.2007	Despatch of a communication from the examining division (Time limit: M04)
	25.05.2007	Reply to a communication from the examining division
	20.05.2010	Despatch of a communication from the examining division (Time limit: M06)
	22.09.2010	Reply to a communication from the examining division
	21.08.2013	Despatch of a communication from the examining division (Time limit: M04)
	23.12.2013	Reply to a communication from the examining division
	25.03.2015	Despatch of a communication from the examining division (Time limit: M04)
	31.07.2015	Reply to a communication from the examining division
	06.11.2015	Despatch of a communication from the examining division (Time limit: M02)
	05.01.2016	Reply to a communication from the examining division
	08.12.2016	Communication of intention to grant the patent
	07.04.2017	Fee for grant paid
	07.04.2017	Fee for publishing/printing paid
	07.04.2017	Receipt of the translation of the claim(s)
Divisional application(s)	The date of the Examining Division's first communication in respect of the earliest application for which a communication has been issued is 18.01.2007
Opposition(s)	22.03.2018	No opposition filed within time limit [2018/22]
Fees paid	Renewal fee
	14.05.2002	Renewal fee patent year 03
	13.05.2003	Renewal fee patent year 04
	13.05.2004	Renewal fee patent year 05
	12.05.2005	Renewal fee patent year 06
	27.03.2006	Renewal fee patent year 07
	14.05.2007	Renewal fee patent year 08
	31.03.2008	Renewal fee patent year 09
	12.05.2009	Renewal fee patent year 10
	31.03.2010	Renewal fee patent year 11
	11.05.2011	Renewal fee patent year 12
	29.03.2012	Renewal fee patent year 13
	10.05.2013	Renewal fee patent year 14
	27.03.2014	Renewal fee patent year 15
	12.05.2015	Renewal fee patent year 16
	10.05.2016	Renewal fee patent year 17
	10.05.2017	Renewal fee patent year 18
Opt-out from the exclusive Tooltip competence of the Unified Patent Court	See the Register of the Unified Patent Court for opt-out data
	Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court.
Documents cited:	Search	[A]JPH1167702 ;
		[A]JPS6187338 ;
		[A]US4278493 (PETVAI STEVE I) [A] 1-11* column 2, line 47 - column 3, line 46; figures 1,2 *;
		[XA]US4357203 (ZELEZ JOSEPH) [X] 11 * the whole document * [A] 1-10;
		[A]DE19627017 (TOSHIBA KAWASAKI KK [JP]) [A] 1-11 * column 4, line 41 - line 66 * * column 8, line 61 - column 10, line 48 * * column 13, line 48 - column 15, line 15; figure 6 *
		[A] - PATENT ABSTRACTS OF JAPAN, (19990630), vol. 1999, no. 08, & JP11067702 A 19990309 (MITSUBISHI ELECTRIC CORP) [A] 1-11 * abstract *
		[A] - PATENT ABSTRACTS OF JAPAN, (19860904), vol. 010, no. 259, Database accession no. (E - 434), & JP61087338 A 19860502 (NEC CORP) [A] 1-11 * abstract *
	Examination	JPH02246246
	by applicant	US4357203

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