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Extract from the Register of European Patents

EP About this file: EP1170868

EP1170868 - Field programmable gate arrays (FPGA) and method for processing FPGA configuration data [Right-click to bookmark this link]
StatusNo opposition filed within time limit
Status updated on  03.07.2009
Database last updated on 06.07.2024
Most recent event   Tooltip30.09.2011Lapse of the patent in a contracting state
New state(s): CY		published on 02.11.2011  [2011/44]
Applicant(s)For all designated states
SUN MICROSYSTEMS, INC.
4150 Network Circle
Santa Clara, California 95054 / US
[2008/35]
Former [2003/17]For all designated states
Sun Microsystems, Inc.
4150 Network Circle
Santa Clara, California 95054 / US
Former [2002/02]For all designated states
SUN MICROSYSTEMS, INC.
901 San Antonio Road
Palo Alto, California 94303 / US
Inventor(s)01 / Garnett, Paul Jeffrey
2 The Rookery
Newton-le-Willows, Merseyside WA12 9PW / GB
 [2002/02]
Representative(s)Haines, Miles John L.S., et al
D Young & Co LLP
120 Holborn
London EC1N 2DY / GB
[N/P]
Former [2002/02]Haines, Miles John, et al
D. Young & Co. 21 New Fetter Lane
London EC4A 1DA / GB
Application number, filing date00305632.204.07.2000
[2002/02]
Filing languageEN
Procedural languageEN
PublicationType: A1 Application with search report 
No.:EP1170868
Date:09.01.2002
Language:EN
[2002/02]
Type: B1 Patent specification 
No.:EP1170868
Date:27.08.2008
Language:EN
[2008/35]
Search report(s)(Supplementary) European search report - dispatched on:EP04.12.2000
ClassificationIPC:H03K19/177, G06F12/14
[2002/02]
CPC:
G06F21/76 (EP); H03K19/1776 (EP); H03K19/17768 (EP)
Designated contracting statesAT,   BE,   CH,   CY,   DE,   DK,   ES,   FI,   FR,   GB,   GR,   IE,   IT,   LI,   LU,   MC,   NL,   PT,   SE [2002/02]
TitleGerman:Anwenderprogrammierbare Gatterfelder (FPGA) und Verfahren zur Bearbeitung von FPGA-Konfigurationsdaten[2002/02]
English:Field programmable gate arrays (FPGA) and method for processing FPGA configuration data[2002/02]
French:Réseaux de portes programmables par l'utilisateur (FPGA) et méthode de traitement de données de configuration FPGA[2002/02]
Examination procedure18.06.2002Examination requested  [2002/34]
26.11.2002Despatch of a communication from the examining division (Time limit: M04)
20.03.2003Reply to a communication from the examining division
13.09.2004Despatch of a communication from the examining division (Time limit: M06)
10.03.2005Reply to a communication from the examining division
24.05.2006Despatch of a communication from the examining division (Time limit: M04)
21.09.2006Reply to a communication from the examining division
19.11.2007Communication of intention to grant the patent
10.03.2008Fee for grant paid
10.03.2008Fee for publishing/printing paid
09.05.2008Despatch of communication that the application is deemed to be withdrawn, reason: fee for grant / fee for printing not paid in time
Opposition(s)28.05.2009No opposition filed within time limit [2009/32]
Request for further processing for:The application is deemed to be withdrawn due to failure to fulfill actions required for granting the patent
30.05.2008Request for further processing filed
30.05.2008Full payment received (date of receipt of payment)
Fees paidRenewal fee
11.07.2002Renewal fee patent year 03
28.07.2003Renewal fee patent year 04
14.07.2004Renewal fee patent year 05
13.07.2005Renewal fee patent year 06
12.07.2006Renewal fee patent year 07
13.07.2007Renewal fee patent year 08
14.07.2008Renewal fee patent year 09
Opt-out from the exclusive  Tooltip
competence of the Unified
Patent Court		 See the Register of the Unified Patent Court for opt-out data
Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court.
Lapses during opposition  TooltipAT27.08.2008
BE27.08.2008
CY27.08.2008
DK27.08.2008
FI27.08.2008
IT27.08.2008
NL27.08.2008
SE27.11.2008
GR28.11.2008
ES08.12.2008
PT27.01.2009
[2011/44]
Former [2010/47]AT27.08.2008
BE27.08.2008
DK27.08.2008
FI27.08.2008
IT27.08.2008
NL27.08.2008
SE27.11.2008
GR28.11.2008
ES08.12.2008
PT27.01.2009
Former [2010/09]AT27.08.2008
BE27.08.2008
DK27.08.2008
FI27.08.2008
IT27.08.2008
NL27.08.2008
SE27.11.2008
ES08.12.2008
PT27.01.2009
Former [2009/39]AT27.08.2008
BE27.08.2008
DK27.08.2008
FI27.08.2008
IT27.08.2008
NL27.08.2008
ES08.12.2008
PT27.01.2009
Former [2009/25]AT27.08.2008
BE27.08.2008
DK27.08.2008
FI27.08.2008
NL27.08.2008
ES08.12.2008
PT27.01.2009
Former [2009/19]AT27.08.2008
BE27.08.2008
DK27.08.2008
FI27.08.2008
NL27.08.2008
ES08.12.2008
Former [2009/15]AT27.08.2008
FI27.08.2008
NL27.08.2008
ES08.12.2008
Former [2009/12]FI27.08.2008
NL27.08.2008
ES08.12.2008
Former [2009/09]NL27.08.2008
ES08.12.2008
Documents cited:Search[X]EP0536943  (PILKINGTON MICRO ELECTRONICS [GB]) [X] 1-6,8-18 * the whole document *;
 [X]US5768372  (SUNG CHIAKANG [US], et al) [X] 1,8-12,14,17 * column 4, line 64 - column 6, line 31; figure 3 *;
 [A]WO9838741  (ACTEL CORP [US]) [A] 19* page 8, line 23 - page 9, line 5 *;
 [XA]WO9946774  (XILINX INC [US]) [X] 1-6,8-11,14-18 * page 1, lines 9-25 * * page 2, line 17 - page 3, line 2 * * page 3, line 23 - page 4, line 12 * * page 5, lines 3-20; figure 1 * * page 4, lines 13-22 * [A] 7;
 [X]US5970142  (ERICKSON CHARLES R [US]) [X] 1,14,17 * column 2, line 65 - column 3, line 51; figure 1 *
ExaminationWO0049717
The EPO accepts no responsibility for the accuracy of data originating from other authorities; in particular, it does not guarantee that it is complete, up to date or fit for specific purposes.