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EP1089168
European procedure
Extract from the Register of European Patents
EP About this file: EP1089168
| EP1089168 - Very long instruction word processor [Right-click to bookmark this link] | Status | No opposition filed within time limit Status updated on 16.09.2011 Database last updated on 29.07.2024 | Most recent event Tooltip | 16.09.2011 | No opposition filed within time limit | published on 19.10.2011 [2011/42] | Applicant(s) | For all designated states FUJITSU LIMITED 1-1, Kamikodanaka 4-chome, Nakahara-ku Kawasaki-shi Kanagawa 211-8588 / JP | [2010/45] |
| Former [2001/14] | For all designated states FUJITSU LIMITED 1-1, Kamikodanaka 4-chome, Nakahara-ku Kawasaki-shi, Kanagawa 211-8588 / JP | Inventor(s) | 01 /
Miyake, Hideo c/o Fujitsu Limited, 1-1, Kamikodanaka 4-chome Nakahara-ku, Kawasaki-shi, Kanagawa 211 / JP | 02 /
Suga, Atsuhiro c/o Fujitsu Limited, 1-1, Kamikodanaka 4-chome Nakahara-ku, Kawasaki-shi, Kanagawa 211 / JP | 03 /
Nakamura, Yasuki c/o Fujitsu Limited, 1-1, Kamikodanaka 4-chome Nakahara-ku, Kawasaki-shi, Kanagawa 211 / JP | 04 /
Takebe, Yoshimasa c/o Fujitsu Limited, 1-1, Kamikodanaka 4-chome Nakahara-ku, Kawasaki-shi, Kanagawa 211 / JP | [2001/14] | Representative(s) | Stebbing, Timothy Charles, et al Haseltine Lake LLP Lincoln House, 5th Floor 300 High Holborn London WC1V 7JH / GB | [N/P] |
| Former [2001/14] | Stebbing, Timothy Charles, et al Haseltine Lake & Co., Imperial House, 15-19 Kingsway London WC2B 6UD / GB | Application number, filing date | 00307646.0 | 05.09.2000 | [2001/14] | Priority number, date | JP19990281957 | 01.10.1999 Original published format: JP 28195799 | [2001/14] | Filing language | EN | Procedural language | EN | Publication | Type: | A2 Application without search report | No.: | EP1089168 | Date: | 04.04.2001 | Language: | EN | [2001/14] | Type: | A3 Search report | No.: | EP1089168 | Date: | 17.10.2001 | [2001/42] | Type: | B1 Patent specification | No.: | EP1089168 | Date: | 10.11.2010 | Language: | EN | [2010/45] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 04.09.2001 | Classification | IPC: | G06F9/38 | [2001/14] | CPC: |
G06F9/382 (EP,US);
G06F9/38 (KR);
G06F9/3802 (EP,US);
G06F9/3853 (EP,US)
| Designated contracting states | DE, FR, GB [2002/27] |
| Former [2001/14] | AT, BE, CH, CY, DE, DK, ES, FI, FR, GB, GR, IE, IT, LI, LU, MC, NL, PT, SE | Title | German: | Prozessor mit sehr langem Befehlswort | [2001/14] | English: | Very long instruction word processor | [2001/14] | French: | Processeur à mot d'instruction très long | [2001/14] | Examination procedure | 08.04.2002 | Examination requested [2002/24] | 18.10.2004 | Despatch of a communication from the examining division (Time limit: M06) | 28.04.2005 | Reply to a communication from the examining division | 13.07.2006 | Despatch of a communication from the examining division (Time limit: M04) | 13.11.2006 | Reply to a communication from the examining division | 21.06.2007 | Despatch of a communication from the examining division (Time limit: M04) | 31.10.2007 | Reply to a communication from the examining division | 01.06.2010 | Communication of intention to grant the patent | 27.09.2010 | Fee for grant paid | 27.09.2010 | Fee for publishing/printing paid | Opposition(s) | 11.08.2011 | No opposition filed within time limit [2011/42] | Fees paid | Renewal fee | 25.09.2002 | Renewal fee patent year 03 | 24.09.2003 | Renewal fee patent year 04 | 27.09.2004 | Renewal fee patent year 05 | 28.09.2005 | Renewal fee patent year 06 | 27.09.2006 | Renewal fee patent year 07 | 26.09.2007 | Renewal fee patent year 08 | 17.03.2008 | Renewal fee patent year 09 | 30.09.2009 | Renewal fee patent year 10 | 29.09.2010 | Renewal fee patent year 11 |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [XY]US5930508 (FARABOSCHI PAOLO [US], et al) [X] 1-4 * column 3, line 16 - line 32 * * column 4, line 57 - column 5, line 35 * [Y] 5,6; | [X]US5787303 (ISHIKAWA TADASHI [JP]) [X] 1,7,8 * abstract * * column 13, line 50 - column 14, line 8 * * column 11, line 3 - line 47 *; | [A]US5497496 (ANDO HIDEKI [JP]) [A] 1,4-6 * abstract * * figure 1 *; | [A]US5761470 (YOSHIDA TOYOHIKO [JP]) [A] 3,5 * column 10, line 14 - line 23 * | [Y] - NAIR R ET AL, "EXPLOITING INSTRUCTION LEVEL PARALLELISM IN PROCESSORS BY CACHING SCHEDULED GROUPS", COMPUTER ARCHITECTURE NEWS,US,ASSOCIATION FOR COMPUTING MACHINERY, NEW YORK, (19970501), vol. 25, no. 2, ISSN 0163-5964, pages 13 - 25, XP000656563 [Y] 5,6 * page 18, column 2, line 3 - page 19, column 2, line 1 * DOI: http://dx.doi.org/10.1145/384286.264125 |