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Extract from the Register of European Patents

EP About this file: EP1139427

EP1139427 - Semiconductor integrated circuit making use of standard cells [Right-click to bookmark this link]
StatusThe application is deemed to be withdrawn
Status updated on  23.11.2018
Database last updated on 24.04.2024
FormerExamination is in progress
Status updated on  23.03.2018
Most recent event   Tooltip11.01.2019Change - classificationpublished on 13.02.2019  [2019/07]
Applicant(s)For all designated states
Kabushiki Kaisha Toshiba
72 Horikawa-cho, Saiwai-ku
Kawasaki-shi / JP
[N/P]
Former [2001/40]For all designated states
KABUSHIKI KAISHA TOSHIBA
72 Horikawa-cho, Saiwai-ku
Kawasaki-shi / JP
Inventor(s)01 / Umemoto, Yasunobu, Toshiba Corp. Intell.Prop.Div.
1-1-1, Shibaura, Minato-ku
Tokyo / JP
02 / Sei, Toshikazu, Toshiba Corp. Intell.Prop.Div.
1-1-1, Shibaura, Minato-ku
Tokyo / JP
03 / Morimoto, Toshiki, Toshiba Corp. Intell.Prop.Div.
1-1-1, Shibaura, Minato-ku
Tokyo / JP
04 / Suzuki, Hiroaki, Toshiba Corp. Intell.Prop.Div.
1-1-1, Shibaura, Minato-ku
Tokyo / JP
 [2001/40]
Representative(s)Hoffmann Eitle
Patent- und Rechtsanwälte PartmbB
Arabellastraße 30
81925 München / DE
[N/P]
Former [2001/40]HOFFMANN - EITLE
Patent- und Rechtsanwälte Arabellastrasse 4
81925 München / DE
Application number, filing date01107445.727.03.2001
[2001/40]
Priority number, dateJP2000008767927.03.2000         Original published format: JP 2000087679
[2001/40]
Filing languageEN
Procedural languageEN
PublicationType: A2 Application without search report 
No.:EP1139427
Date:04.10.2001
Language:EN
[2001/40]
Type: A3 Search report 
No.:EP1139427
Date:27.06.2007
[2007/26]
Search report(s)(Supplementary) European search report - dispatched on:EP31.05.2007
ClassificationIPC:H01L27/118, H01L27/02, G06F17/50
[2007/26]
CPC:
H01L27/11807 (EP,US); H01L21/82 (KR); H01L27/0211 (EP,US)
Former IPC [2001/40]H01L27/118
Designated contracting statesDE,   FR,   GB [2008/10]
Former [2001/40]AT,  BE,  CH,  CY,  DE,  DK,  ES,  FI,  FR,  GB,  GR,  IE,  IT,  LI,  LU,  MC,  NL,  PT,  SE,  TR 
TitleGerman:Integrierter Halbleiterschaltkreis mit Standardzellenverwendung[2001/40]
English:Semiconductor integrated circuit making use of standard cells[2001/40]
French:Circuit intégré à semi-conducteur employant des cellules du type standard[2001/40]
Examination procedure27.03.2001Examination requested  [2001/40]
21.09.2007Despatch of a communication from the examining division (Time limit: M06)
28.12.2007Loss of particular rights, legal effect: designated state(s)
01.02.2008Despatch of communication of loss of particular rights: designated state(s) AT, BE, CH, CY, DK, ES, FI, GR, IE, IT, LU, MC, NL, PT, SE, TR
27.03.2008Reply to a communication from the examining division
28.07.2011Despatch of a communication from the examining division (Time limit: M02)
16.09.2011Reply to a communication from the examining division
13.03.2018Despatch of a communication from the examining division (Time limit: M04)
24.07.2018Application deemed to be withdrawn, date of legal effect  [2018/52]
22.08.2018Despatch of communication that the application is deemed to be withdrawn, reason: reply to the communication from the examining division not received in time  [2018/52]
Divisional application(s)The date of the Examining Division's first communication in respect of the earliest application for which a communication has been issued is  21.09.2007
Fees paidRenewal fee
11.03.2003Renewal fee patent year 03
15.03.2004Renewal fee patent year 04
14.03.2005Renewal fee patent year 05
09.03.2006Renewal fee patent year 06
14.03.2007Renewal fee patent year 07
14.03.2008Renewal fee patent year 08
13.03.2009Renewal fee patent year 09
15.03.2010Renewal fee patent year 10
15.03.2011Renewal fee patent year 11
14.03.2012Renewal fee patent year 12
11.03.2013Renewal fee patent year 13
12.03.2014Renewal fee patent year 14
10.03.2015Renewal fee patent year 15
10.03.2016Renewal fee patent year 16
10.03.2017Renewal fee patent year 17
13.03.2018Renewal fee patent year 18
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Documents cited:Search[A]JPS618969  (NIPPON ELECTRIC CO) [A] 1-7* abstract *;
 [A]US4884115  (MICHEL PETRA [DE], et al) [A] 1-10 * the whole document *;
 [Y]US5219770  (SHIRATO TAKEHIDE [JP], et al) [Y] 1-7 * abstract * * column 1, line 16 - line 26 * * column 2, line 15 - line 19 * * column 2, line 40 - line 45 * * column 3, line 25 - line 64 *;
 [Y]JPH07152796  (KAWASAKI STEEL CO) [Y] 1-7 * abstract *;
 [Y]US5901065  (GURUSWAMY MOHAN [US], et al) [Y] 1-10 * abstract * * column 3, line 30 - column 7, line 67 *;
 [XY]US5981987  (BRUNOLLI MICHAEL J [US], et al) [X] 8-10 * abstract * * column 5, line 30 - line 67 * [Y] 1-7;
 [Y]  - KRISHNA B ET AL, "Diffusion sharing across cell boundaries in cell based design", CIRCUITS AND SYSTEMS, 1996., IEEE 39TH MIDWEST SYMPOSIUM ON AMES, IA, USA 18-21 AUG. 1996, NEW YORK, NY, USA,IEEE, US, (19960818), vol. 1, ISBN 0-7803-3636-4, pages 349 - 352, XP010222891 [Y] 1-10 * the whole document *

DOI:   http://dx.doi.org/10.1109/MWSCAS.1996.594170
 [A]  - GURUSWAMY M ET AL, "CELLERITY: A Fully Automatic Layout Synthesis System For Standard Cell Libraries", PROCEEDINGS OF THE DESIGN AUTOMATION CONFERENCE. ANAHEIM, JUNE 9 - 13, 1997, NEW YORK, ACM, US, (19970609), vol. CONF. 34, ISBN 0-7803-4093-0, pages 327 - 332, XP010227603 [A] 1-10 * the whole document *

DOI:   http://dx.doi.org/10.1145/266021.266126
The EPO accepts no responsibility for the accuracy of data originating from other authorities; in particular, it does not guarantee that it is complete, up to date or fit for specific purposes.