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EP1158403
European procedure
Extract from the Register of European Patents
EP About this file: EP1158403
| EP1158403 - FPGA with configurable clock lines [Right-click to bookmark this link] | Status | No opposition filed within time limit Status updated on 27.02.2004 Database last updated on 06.07.2024 | Most recent event Tooltip | 27.02.2004 | No opposition filed within time limit | published on 14.04.2004 [2004/16] | Applicant(s) | For all designated states ATMEL CORPORATION 2325 Orchard Parkway San Jose, CA 95131 / US | [N/P] |
| Former [2001/48] | For all designated states ATMEL CORPORATION 2325 Orchard Parkway San Jose, California 95131 / US | Inventor(s) | 01 /
Furtek, Frederick C. 2470 Sharon Oak Drive Menlo Park, California 94025 / US | 02 /
Mason, Martin T. 2249 Cherrystone Drive San Jose, California 95128 / US | 03 /
Luking, Robert B. 38 Delrey Avenue Catonsville, Maryland 21228 / US | [2001/48] | Representative(s) | Käck, Jürgen Patentanwälte Kahler Käck Mollekopf Vorderer Anger 239 86899 Landsberg/Lech / DE | [N/P] |
| Former [2001/48] | Käck, Jürgen Kahler, Käck, Fiener et Col. Vorderer Anger 268 86899 Landsberg / DE | Application number, filing date | 01107758.3 | 09.05.1997 | [2001/48] | Priority number, date | US19960650477 | 20.05.1996 Original published format: US 650477 | [2001/48] | Filing language | EN | Procedural language | EN | Publication | Type: | A1 Application with search report | No.: | EP1158403 | Date: | 28.11.2001 | Language: | EN | [2001/48] | Type: | B1 Patent specification | No.: | EP1158403 | Date: | 23.04.2003 | Language: | EN | [2003/17] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 21.08.2001 | Classification | IPC: | G06F9/455, H03K19/177, H03K19/173 | [2001/48] | CPC: |
H03K19/17736 (EP,US);
G06F13/00 (KR);
H03K19/1735 (EP,US);
H03K19/1737 (EP,US);
H03K19/17728 (EP,US)
| Designated contracting states | DE, FR, GB, IT, NL [2001/48] | Title | German: | FPGA mit konfigurierbaren Taktleitungen | [2001/48] | English: | FPGA with configurable clock lines | [2001/48] | French: | FPGA avec des lignes d'horloge configurables | [2001/48] | Examination procedure | 23.11.2001 | Amendment by applicant (claims and/or description) | 15.03.2002 | Examination requested [2002/22] | 24.10.2002 | Communication of intention to grant the patent | 24.01.2003 | Fee for grant paid | 24.01.2003 | Fee for publishing/printing paid | Parent application(s) Tooltip | EP97926441.3 / EP0846289 | Opposition(s) | 26.01.2004 | No opposition filed within time limit [2004/16] | Fees paid | Renewal fee | 03.08.2001 | Renewal fee patent year 03 | 03.08.2001 | Renewal fee patent year 04 | 03.08.2001 | Renewal fee patent year 05 | 31.05.2002 | Renewal fee patent year 06 |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [X]EP0575050 (ACTEL CORP [US]) [X] 1,2,2 * column 2, line 41 - column 3, line 1; claim 1 * * column 6, line 32 - column 6, line 41 *; | [X]EP0596658 (AMERICAN TELEPHONE & TELEGRAPH [US]) [X] 1* column 4, line 37 - column 4, line 51; figure 2 * |