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EP1158524
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EP About this file: EP1158524
| EP1158524 - Semiconductor memory device having a boosted voltage generating circuit [Right-click to bookmark this link] | Status | The application has been withdrawn Status updated on 03.07.2009 Database last updated on 03.06.2024 | Most recent event Tooltip | 03.07.2009 | Withdrawal of application | published on 05.08.2009 [2009/32] | Applicant(s) | For all designated states Kabushiki Kaisha Toshiba 72, Horikawa-cho, Saiwai-ku Kawasaki-shi Kanagawa-ken 210-8572 / JP | [N/P] |
| Former [2001/48] | For all designated states KABUSHIKI KAISHA TOSHIBA 72, Horikawa-cho, Saiwai-ku Kawasaki-shi, Kanagawa-ken 210-8572 / JP | Inventor(s) | 01 /
Tanzawa, Toru, Intellectual Property Division Kabushiki Kaisha Toshiba, 1-1 Shibaura 1-chome Minato-ku, Tokyo 105-8001 / JP | 02 /
Miyaba, Takeshi, Intellectual Property Division Kabushiki Kaisha Toshiba, 1-1 Shibaura 1-chome Minato-ku, Tokyo 105-8001 / JP | 03 /
Atsumi, Shigeru, Intellectual Property Division Kabushiki Kaisha Toshiba, 1-1 Shibaura 1-chome Minato-ku, Tokyo 105-8001 / JP | [2001/48] | Representative(s) | Hoffmann Eitle Patent- und Rechtsanwälte PartmbB Arabellastrasse 30 81925 München / DE | [N/P] |
| Former [2001/48] | HOFFMANN - EITLE Patent- und Rechtsanwälte Arabellastrasse 4 81925 München / DE | Application number, filing date | 01112062.3 | 25.05.2001 | [2001/48] | Priority number, date | JP20000154983 | 25.05.2000 Original published format: JP 2000154983 | [2001/48] | Filing language | EN | Procedural language | EN | Publication | Type: | A1 Application with search report | No.: | EP1158524 | Date: | 28.11.2001 | Language: | EN | [2001/48] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 06.09.2001 | Classification | IPC: | G11C5/14, G11C16/12 | [2001/48] | CPC: |
G11C5/145 (EP,US);
G11C16/12 (EP,US);
G11C16/30 (EP,US);
G11C5/14 (EP,US);
G11C5/147 (EP,US)
| Designated contracting states | DE, FR, GB [2002/33] |
| Former [2001/48] | AT, BE, CH, CY, DE, DK, ES, FI, FR, GB, GR, IE, IT, LI, LU, MC, NL, PT, SE, TR | Title | German: | Halbleiterspeicher mit Spannungserhöhungsschaltung | [2001/48] | English: | Semiconductor memory device having a boosted voltage generating circuit | [2001/48] | French: | Mémoire a semiconducteur avec circuit élévateur de tension | [2001/48] | Examination procedure | 25.05.2001 | Examination requested [2001/48] | 30.06.2009 | Application withdrawn by applicant [2009/32] | Fees paid | Renewal fee | 13.05.2003 | Renewal fee patent year 03 | 13.05.2004 | Renewal fee patent year 04 | 12.05.2005 | Renewal fee patent year 05 | 23.03.2006 | Renewal fee patent year 06 | 14.05.2007 | Renewal fee patent year 07 | 28.03.2008 | Renewal fee patent year 08 | 12.05.2009 | Renewal fee patent year 09 |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [A]US5483486 (JAVANIFARD JAHANSHIR J [US], et al) [A] 1* column 18, line 7 - column 19, line 29; figures 13A,13 *; | [A]US6041012 (BANBA HIRONORI [JP], et al) [A] 1,10 * abstract * |