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Extract from the Register of European Patents

EP About this file: EP1198043

EP1198043 - Method of fabricating a III-V compound semiconductor device with an Aluminium-compound layer [Right-click to bookmark this link]
StatusThe application is deemed to be withdrawn
Status updated on  10.06.2005
Database last updated on 14.06.2024
Most recent event   Tooltip10.06.2005Application deemed to be withdrawnpublished on 27.07.2005  [2005/30]
Applicant(s)For all designated states
THE FURUKAWA ELECTRIC CO., LTD.
6-1, Marunouchi 2-chome, Chiyoda-ku
Tokyo / JP
[N/P]
Former [2002/16]For all designated states
THE FURUKAWA ELECTRIC CO., LTD.
6-1, Marunouchi 2-chome, Chiyoda-ku
Tokyo / JP
Inventor(s)01 / Arakawa, Satoshi
The Furukawa Electric Co., Ltd., 2-6-1, Marunouchi
Chiyoda-ku, Tokyo / JP
02 / Kasukawa, Akihiko
The Furukawa Electric Co., Ltd., 2-6-1, Marunouchi
Chiyoda-ku, Tokyo / JP
 [2002/16]
Representative(s)Modiano, Guido, et al
Modiano, Josif, Pisanty & Staub Ltd., Baaderstrasse 3
80469 München / DE
[N/P]
Former [2002/16]Modiano, Guido, Dr.-Ing., et al
Modiano, Josif, Pisanty & Staub, Baaderstrasse 3
80469 München / DE
Application number, filing date01123215.401.10.2001
[2002/16]
Priority number, dateJP2000030763706.10.2000         Original published format: JP 2000307637
[2002/16]
Filing languageEN
Procedural languageEN
PublicationType: A2 Application without search report 
No.:EP1198043
Date:17.04.2002
Language:EN
[2002/16]
Type: A3 Search report 
No.:EP1198043
Date:28.04.2004
[2004/18]
Search report(s)(Supplementary) European search report - dispatched on:EP15.03.2004
ClassificationIPC:H01S5/22, H01L33/00, H01L21/306, H01S5/223
[2004/18]
CPC:
H01L21/3065 (EP,US); H01L21/02392 (EP,US); H01L21/02461 (EP,US);
H01L21/02463 (EP,US); H01L21/02505 (EP,US); H01L21/02543 (EP,US);
H01L21/02546 (EP,US); H01L21/0262 (EP,US); H01L21/02639 (EP,US);
H01L21/02647 (EP,US); H01L33/0062 (EP,US); H01S5/2081 (EP,US);
H01S5/2275 (EP,US) (-)
Former IPC [2002/16]H01S5/22, H01S5/24, H01S5/223, H01L33/00, H01L21/306
Designated contracting states(deleted) [2005/03]
Former [2002/16]AT,  BE,  CH,  CY,  DE,  DK,  ES,  FI,  FR,  GB,  GR,  IE,  IT,  LI,  LU,  MC,  NL,  PT,  SE,  TR 
TitleGerman:Verfahren zur Herstellung eines III-V Verbindungshalbleiter-Bauelementes mit einer Aluminium-basierten Verbindungsschicht[2002/16]
English:Method of fabricating a III-V compound semiconductor device with an Aluminium-compound layer[2002/16]
French:Méthode de fabrication d'un dispositif semiconducteur en composé III-V comprenant une couche d'un composé d'Aluminium[2002/16]
Examination procedure29.10.2004Application deemed to be withdrawn, date of legal effect  [2005/30]
22.02.2005Despatch of communication that the application is deemed to be withdrawn, reason: examination fee not paid in time  [2005/30]
Fees paidRenewal fee
24.10.2003Renewal fee patent year 03
Penalty fee
Penalty fee Rule 85a EPC 1973
06.12.2004AT   M01   Not yet paid
06.12.2004BE   M01   Not yet paid
06.12.2004CH   M01   Not yet paid
06.12.2004CY   M01   Not yet paid
06.12.2004DE   M01   Not yet paid
06.12.2004DK   M01   Not yet paid
06.12.2004ES   M01   Not yet paid
06.12.2004FI   M01   Not yet paid
06.12.2004FR   M01   Not yet paid
06.12.2004GB   M01   Not yet paid
06.12.2004GR   M01   Not yet paid
06.12.2004IE   M01   Not yet paid
06.12.2004IT   M01   Not yet paid
06.12.2004LU   M01   Not yet paid
06.12.2004MC   M01   Not yet paid
06.12.2004NL   M01   Not yet paid
06.12.2004PT   M01   Not yet paid
06.12.2004SE   M01   Not yet paid
06.12.2004TR   M01   Not yet paid
Penalty fee Rule 85b EPC 1973
06.12.2004M01   Not yet paid
Additional fee for renewal fee
31.10.200404   M06   Not yet paid
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Documents cited:Search[Y]EP0374036  (FUJITSU LTD [JP]) [Y] 1-3,5-7,11 * column 8, line 1 - column 9, line 2 *;
 [X]EP0709902  (MITSUBISHI CHEM CORP [JP]) [X] 1,2,4-7,10-13,15-17 * column 5, line 12 - column 6, line 58 * * column 9, line 51 - column 10, line 52* * Figures 2a - 2d, 5 *;
 [Y]US5942447  (MIYAKUNI SHINICHI [JP]) [Y] 1-3,5-7,11 * column 13, line 24 - line 30 * * column 15, line 22 - line 55 *;
 [XY]  - HOU H Q ET AL, "In situ etching of GaAs by AsCl3 for regrowth on AlGaAs in metalorganic vapor-phase epitaxy", JOURNAL OF CRYSTAL GROWTH, NORTH-HOLLAND PUBLISHING CO. AMSTERDAM, NL, (19981215), vol. 195, no. 1-4, ISSN 0022-0248, pages 199 - 204, XP004154260 [X] 12-14,16,17 * the whole document * [Y] 1-3,5-7,11

DOI:   http://dx.doi.org/10.1016/S0022-0248(98)00733-7
 [PX]  - ARAKAWA S ET AL, "In-situ etching of semiconductor with CBr4 in MOCVD reactor", CONFERENCE PROCEEDINGS. 2001 INTERNATIONAL CONFERENCE ON INDIUM PHOSPHIDE AND RELATED MATERIALS. IPRM. NARA, JAPAN, MAY 14 - 18, 2001, INTERNATIONAL CONFERENCE ON INDIUM PHOSPHIDE AND RELATED MATERIALS, NEW YORK, NY: IEEE, US, (20010514), vol. CONF. 13, ISBN 0-7803-6700-6, pages 71 - 74, XP010546976 [PX] 1-17 * the whole document *

DOI:   http://dx.doi.org/10.1109/ICIPRM.2001.929021
 [A]  - INOUE Y ET AL, "FABRICATION OF ALXGA1-XAS BURIED HETEROSTRUCTURE LASER DIODES BY IN-SITU GAS ETCHING AND SELECTIVE-AREA METALORGANIC VAPOR PHASE EPITAXY", JOURNAL OF CRYSTAL GROWTH, NORTH-HOLLAND PUBLISHING CO. AMSTERDAM, NL, (19941202), vol. 145, no. 1/4, ISSN 0022-0248, pages 881 - 885, XP000511799

DOI:   http://dx.doi.org/10.1016/0022-0248(94)91157-6
 [A]  - IKAWA S ET AL, "AIGAAS-GAAS BURIED HETEROSTRUCTURE LASER WITH VERTICALLY ETCHED FACETS AND WIDE-BANDGAP OPTICAL WINDOWS BY IN SITU C2H5CI GAS-PHASEETCHING AND MOCVD REGROWTH", IEEE PHOTONICS TECHNOLOGY LETTERS, IEEE INC. NEW YORK, US, (19970601), vol. 9, no. 6, ISSN 1041-1135, pages 719 - 721, XP000692401

DOI:   http://dx.doi.org/10.1109/68.584968
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