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Extract from the Register of European Patents

EP About this file: EP1220587

EP1220587 - Process for contemporaneous manufacture and interconnection between adjoining wiring boards [Right-click to bookmark this link]
StatusThe application is deemed to be withdrawn
Status updated on  20.05.2005
Database last updated on 14.09.2024
Most recent event   Tooltip20.05.2005Application deemed to be withdrawnpublished on 06.07.2005  [2005/27]
Applicant(s)For all designated states
Xerox Corporation
Xerox Square - 20 A, 100 Clinton Avenue South Rochester
New York 14644 / US
[N/P]
Former [2002/27]For all designated states
Xerox Corporation
Patent Department, Xerox Square - 20 A, 100 Clinton Avenue South
Rochester, New York 14644 / US
Inventor(s)01 / Reijnders, Harry j M.
Laurahof 2
5801 JE Venray / NL
 [2002/27]
Representative(s)Grünecker Patent- und Rechtsanwälte PartG mbB
Leopoldstrasse 4
80802 München / DE
[N/P]
Former [2002/27]Grünecker, Kinkeldey, Stockmair & Schwanhäusser Anwaltssozietät
Maximilianstrasse 58
80538 München / DE
Application number, filing date01130439.120.12.2001
[2002/27]
Priority number, dateUS2000074677421.12.2000         Original published format: US 746774
[2002/27]
Filing languageEN
Procedural languageEN
PublicationType: A2 Application without search report 
No.:EP1220587
Date:03.07.2002
Language:EN
[2002/27]
Type: A3 Search report 
No.:EP1220587
Date:14.04.2004
[2004/16]
Search report(s)(Supplementary) European search report - dispatched on:EP03.03.2004
ClassificationIPC:H05K3/00, H05K3/36
[2004/15]
CPC:
H05K1/148 (EP,US); H05K3/0052 (EP,US); H05K2201/09036 (EP,US);
H05K2201/0909 (EP,US); H05K2201/10287 (EP,US); H05K2203/0195 (EP,US);
H05K2203/302 (EP,US); Y10T29/49155 (EP,US) (-)
Former IPC [2002/27]H05K3/36, H05K3/00
Designated contracting states(deleted) [2005/01]
Former [2002/27]AT,  BE,  CH,  CY,  DE,  DK,  ES,  FI,  FR,  GB,  GR,  IE,  IT,  LI,  LU,  MC,  NL,  PT,  SE,  TR 
TitleGerman:Verfahren zur gleichzeitigen Herstellung und Verbindung von angrenzenden Leiterplatten[2002/27]
English:Process for contemporaneous manufacture and interconnection between adjoining wiring boards[2002/27]
French:Procédé de fabrication et d'interconnection simultanée de panneaux à circuit adjacents[2002/27]
Examination procedure15.10.2004Application deemed to be withdrawn, date of legal effect  [2005/27]
08.02.2005Despatch of communication that the application is deemed to be withdrawn, reason: examination fee not paid in time  [2005/27]
Fees paidRenewal fee
02.01.2004Renewal fee patent year 03
Penalty fee
Penalty fee Rule 85a EPC 1973
22.11.2004DE   M01   Not yet paid
22.11.2004FR   M01   Not yet paid
22.11.2004GB   M01   Not yet paid
Penalty fee Rule 85b EPC 1973
22.11.2004M01   Not yet paid
Additional fee for renewal fee
31.12.200404   M06   Not yet paid
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Patent Court		 See the Register of the Unified Patent Court for opt-out data
Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court.
Documents cited:Search[XY]US4227238  (SAITO MASASHI) [X] 1-3,5,7,9,10 * column 6, line 31 - column 9, line 6; figures 7-15 * [Y] 6;
 [AY]GB840762  (EMI LTD) [A] 1,10 * page 2, line 119 - page 3, line 22; figure - * [Y] 6;
 [X]US4335272  (PITTENGER DANIEL I) [X] 1,2,4,5,7,9,10 * the whole document *;
 [X]JPH10224007  ;
 [X]JPH10224006  ;
 [X]GB2061623  (TEKTRONIX INC) [X] 1,2,4,5,7,9,10 * the whole document *;
 [X]DE3743163  (OLYMPIA AEG [DE]) [X] 1,2,5,7,9,10 * the whole document *
 [X]  - PATENT ABSTRACTS OF JAPAN, (19981130), vol. 1998, no. 13, & JP10224007 A 19980821 (AIWA CO LTD) [X] 1-3,5,7,9,10 * abstract *
 [X]  - PATENT ABSTRACTS OF JAPAN, (19981130), vol. 1998, no. 13, & JP10224006 A 19980821 (AIWA CO LTD) [X] 1,2,5-10 * abstract *
The EPO accepts no responsibility for the accuracy of data originating from other authorities; in particular, it does not guarantee that it is complete, up to date or fit for specific purposes.