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Extract from the Register of European Patents

EP About this file: EP1122776

EP1122776 - Process for producing semiconductor chips [Right-click to bookmark this link]
Former [2001/32]Process for producing semiconductor chip
[2006/37]
StatusNo opposition filed within time limit
Status updated on  08.02.2008
Database last updated on 07.06.2024
Most recent event   Tooltip08.02.2008No opposition filed within time limitpublished on 12.03.2008  [2008/11]
Applicant(s)For all designated states
Lintec Corporation
23-23, Honcho, Itabashi-ku
Tokyo 173-0001 / JP
[2007/14]
Former [2001/32]For all designated states
Lintec Corporation
23-23, Honcho, Itabashi-ku
Tokyo 173-0001 / JP
Inventor(s)01 / Noguchi, Hayato
376, Kanai, Agatsuma-machi, Agatsuma-gun
Gunma / JP
02 / Ebe, Kazuyoshi
1375-19, Shimonoda, Shiraoka-machi
Minamisaitama-gun, Saitama / JP
 [2006/40]
Former [2001/40]01 / Noguchi, Hayato
Agatsuma-machi, Agatsuma-gun
Gunma / JP
02 / Ebe, Kazuyoshi
1375-19, Shimonoda, Shiraoka-machi
Minamisaitama-gun, Saitama / JP
Former [2001/32]01 / Noguchi, Hayato
1-22-17, Shimmei
urawa-shi, Saitama / JP
02 / Ebe, Kazuyoshi
1375-19, Shimonoda, Shiraoka-machi
Minamisaitama-gun, Saitama / JP
Representative(s)Piésold, Alexander James
Dehns
St Bride's House
10 Salisbury Square
London EC4Y 8JD / GB
[N/P]
Former [2001/32]Piésold, Alexander J.
Frank B. Dehn & Co., European Patent Attorneys, 179 Queen Victoria Street
London EC4V 4EL / GB
Application number, filing date01301093.907.02.2001
[2001/32]
Priority number, dateJP2000002870207.02.2000         Original published format: JP 2000028702
[2001/32]
Filing languageEN
Procedural languageEN
PublicationType: A2 Application without search report 
No.:EP1122776
Date:08.08.2001
Language:EN
[2001/32]
Type: A3 Search report 
No.:EP1122776
Date:28.01.2004
[2004/05]
Type: B1 Patent specification 
No.:EP1122776
Date:04.04.2007
Language:EN
[2007/14]
Type: B8 Corrected title page of specification 
No.:EP1122776
Date:06.06.2007
[2007/23]
Search report(s)(Supplementary) European search report - dispatched on:EP17.12.2003
ClassificationIPC:H01L21/82, H01L21/58, H01L21/68, H01L21/78, H01L21/00
[2004/05]
CPC:
H01L21/6836 (EP,US); H01L21/78 (EP,KR,US); H01L2221/68327 (EP,US)
Former IPC [2001/32]H01L21/82
Designated contracting statesDE,   FR,   GB,   IT,   PT [2004/43]
Former [2001/32]AT,  BE,  CH,  CY,  DE,  DK,  ES,  FI,  FR,  GB,  GR,  IE,  IT,  LI,  LU,  MC,  NL,  PT,  SE,  TR 
TitleGerman:Verfahren zur Herstellung von Halbleiterchips[2001/32]
English:Process for producing semiconductor chips[2006/37]
French:Procédé de fabrication de puces semiconductrices[2007/19]
Former [2001/32]Process for producing semiconductor chip
Former [2001/32]Procédé de fabrication de chips semiconducteurs
Examination procedure22.04.2004Examination requested  [2004/25]
06.07.2004Despatch of a communication from the examining division (Time limit: M04)
16.11.2004Reply to a communication from the examining division
07.09.2006Communication of intention to grant the patent
15.01.2007Fee for grant paid
15.01.2007Fee for publishing/printing paid
Opposition(s)07.01.2008No opposition filed within time limit [2008/11]
Fees paidRenewal fee
26.02.2003Renewal fee patent year 03
23.02.2004Renewal fee patent year 04
24.02.2005Renewal fee patent year 05
23.02.2006Renewal fee patent year 06
21.02.2007Renewal fee patent year 07
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Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court.
Documents cited:Search[A]EP0884766  (LINTEC CORP [JP]) [A] 1-3 * column 2, lines 15-40 * * column 6, lines 33-44 * * column 7, lines 27-47 * * figures 4-6 *;
 [A]US5641714  (YAMANAKA HIDEO [JP]) [A] 1-3 * figure 4A *;
 [A]US5824177  (YOSHIHARA SHINJI [JP], et al) [A] 1-3 * the whole document *;
 [A]US5525422  (SPIES MANFRED [DE], et al) [A] 1-3 * the whole document *
The EPO accepts no responsibility for the accuracy of data originating from other authorities; in particular, it does not guarantee that it is complete, up to date or fit for specific purposes.