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Extract from the Register of European Patents

EP About this file: EP1379977

EP1379977 - HDL PREPROCESSOR [Right-click to bookmark this link]
StatusThe application is deemed to be withdrawn
Status updated on  04.07.2014
Database last updated on 02.09.2024
Most recent event   Tooltip04.07.2014Application deemed to be withdrawnpublished on 06.08.2014  [2014/32]
Applicant(s)For all designated states
Mentor Graphics Corporation
8005 S.W. Boeckman Road
Wilsonville, OR 97070-7777 / US
[N/P]
Former [2004/03]For all designated states
Mentor Graphics Corporation
8005 S.W. Boeckman Road
Wilsonville, Oregon 97070-7777 / US
Inventor(s)01 / POCHAYEVETS, Olexandr
Berckhauserstrasse 42
90409 Nuernberg / DE
02 / SIEGL, Johann
Georg-Simon-Ohm-Fachhochschule
Kesslerplatz, 90489 Nuernberg / DE
03 / EICHELE, Herbert
Georg-Simon-Ohm-Fachhochschule
Kesslerplatz, 90489 Nuernberg / DE
 [2004/03]
Representative(s)Vossius & Partner Patentanwälte Rechtsanwälte mbB
Siebertstrasse 3
81675 München / DE
[N/P]
Former [2008/35]Vossius & Partner
Siebertstrasse 3
81675 München / DE
Former [2004/03]VOSSIUS & PARTNER
Siebertstrasse 4
81675 München / DE
Application number, filing date01924969.711.04.2001
[2004/03]
WO2001US11931
Filing languageEN
Procedural languageEN
PublicationType: A1 Application with search report
No.:WO02084538
Date:24.10.2002
Language:EN
[2002/43]
Type: A1 Application with search report 
No.:EP1379977
Date:14.01.2004
Language:EN
The application published by WIPO in one of the EPO official languages on 24.10.2002 takes the place of the publication of the European patent application.
[2004/03]
Search report(s)International search report - published on:EP24.10.2002
ClassificationIPC:G06F17/50
[2004/03]
CPC:
G06F30/30 (EP)
Designated contracting statesAT,   BE,   CH,   CY,   DE,   DK,   ES,   FI,   FR,   GB,   GR,   IE,   IT,   LI,   LU,   MC,   NL,   PT,   SE,   TR [2004/03]
Extension statesALNot yet paid
LTNot yet paid
LVNot yet paid
MKNot yet paid
RONot yet paid
SINot yet paid
TitleGerman:HDL-VORPROZESSOR[2004/03]
English:HDL PREPROCESSOR[2004/03]
French:PREPROCESSEUR HDL[2004/03]
Entry into regional phase07.11.2003National basic fee paid 
07.11.2003Designation fee(s) paid 
07.11.2003Examination fee paid 
Examination procedure07.11.2002Request for preliminary examination filed
International Preliminary Examining Authority: US
07.11.2003Examination requested  [2004/03]
13.12.2006Despatch of a communication from the examining division (Time limit: M06)
09.05.2007Reply to a communication from the examining division
20.05.2009Despatch of a communication from the examining division (Time limit: M04)
29.09.2009Reply to a communication from the examining division
31.03.2011Despatch of a communication from the examining division (Time limit: M04)
03.08.2011Reply to a communication from the examining division
24.01.2012Despatch of a communication from the examining division (Time limit: M06)
27.07.2012Reply to a communication from the examining division
05.09.2012Despatch of a communication from the examining division (Time limit: M06)
14.03.2013Reply to a communication from the examining division
26.08.2013Despatch of a communication from the examining division (Time limit: M06)
06.03.2014Application deemed to be withdrawn, date of legal effect  [2014/32]
01.04.2014Despatch of communication that the application is deemed to be withdrawn, reason: reply to the communication from the examining division not received in time  [2014/32]
Divisional application(s)The date of the Examining Division's first communication in respect of the earliest application for which a communication has been issued is  13.12.2006
Fees paidRenewal fee
07.11.2003Renewal fee patent year 03
15.04.2004Renewal fee patent year 04
13.04.2005Renewal fee patent year 05
17.03.2006Renewal fee patent year 06
12.04.2007Renewal fee patent year 07
18.03.2008Renewal fee patent year 08
07.04.2009Renewal fee patent year 09
15.03.2010Renewal fee patent year 10
06.04.2011Renewal fee patent year 11
19.03.2012Renewal fee patent year 12
26.03.2013Renewal fee patent year 13
25.03.2014Renewal fee patent year 14
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Cited inInternational search[X]US6120549  (GOSLIN GREGORY R [US], et al) [X] 1-19 * column 2, line 15 - line 26 * * column 2, line 46 - column 5, line 23 * * figure 2 *;
 [X]EP0834823  (VLSI TECHNOLOGY INC [US]) [X] 1-19 * page 5, line 24 - page 7, line 18 * * figures 3-6 *
 [X]  - SEZER S ET AL, "VHDL package GUI", IEE SEMINAR ON INTELLECTUAL PROPERTY (REF. NO.00/082), IEE SEMINAR ON INTELLECTUAL PROPERTY, EDINBURGH, UK, 6 JULY 2000, 2000, London, UK, IEE, UK, pages 5/1 - 5, XP001023908 [X] 1-19 * paragraphs [0004] , [0005] * * figures 1,2 *
 [X]  - BERGAMASCHI R ET AL, "Coral-automating the design of systems-on-chip using cores", PROCEEDINGS OF THE IEEE 2000 CUSTOM INTEGRATED CIRCUITS CONFERENCE (CAT. NO.00CH37044), PROCEEDINGS OF THE IEEE 2000 CUSTOM INTEGRATED CIRCUITS CONFERENCE, ORLANDO, FL, USA, 21-24 MAY 2000, 2000, Piscataway, NJ, USA, IEEE, USA, ISBN 0-7803-5809-0, pages 109 - 112, XP002186200 [X] 1-19 * paragraphs [002A] , [002F] * * figure 1 *
by applicantWO0046704
The EPO accepts no responsibility for the accuracy of data originating from other authorities; in particular, it does not guarantee that it is complete, up to date or fit for specific purposes.