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Extract from the Register of European Patents

EP About this file: EP1334512

EP1334512 - FET WITH NOTCHED GATE AND METHOD OF MANUFACTURING THE SAME [Right-click to bookmark this link]
StatusThe application has been withdrawn
Status updated on  25.09.2009
Database last updated on 24.08.2024
Most recent event   Tooltip25.09.2009Withdrawal of applicationpublished on 28.10.2009  [2009/44]
Applicant(s)For all designated states
International Business Machines Corporation
New Orchard Road
Armonk, NY 10504 / US
[N/P]
Former [2003/33]For all designated states
International Business Machines Corporation
New Orchard Road
Armonk, NY 10504 / US
Inventor(s)01 / FURUKAWA, Toshiharu
9 Oakwood Lane
Essex Junction, VT 05452 / US
02 / HAKEY, Mark
15 Bellows Street
Fairfax, VT 05454 / US
03 / HOLMES, Steven
127 Devino Road
Milton, VT 05468 / US
04 / HORAK, David
47 Briar Lane
Essex Junction, VT 05452 / US
05 / NOWAK, Edward
8 Windridge Road
Essex Junction, VT 05452 / US
 [2003/33]
Representative(s)Burt, Roger James
IBM United Kingdom Limited Intellectual Property Department Hursley Park Winchester
Hampshire SO21 2JN / GB
[N/P]
Former [2003/33]Burt, Roger James, Dr.
IBM United Kingdom Limited, Intellectual Property Law, MP 110, Hursley Park, Hursley
Winchester, Hampshire SO21 2JN / GB
Application number, filing date01983677.413.11.2001
[2003/33]
WO2001GB05015
Priority number, dateUS2000071383015.11.2000         Original published format: US 713830
[2003/33]
Filing languageEN
Procedural languageEN
PublicationType: A1 Application with search report
No.:WO0241383
Date:23.05.2002
Language:EN
[2002/21]
Type: A1 Application with search report 
No.:EP1334512
Date:13.08.2003
Language:EN
The application published by WIPO in one of the EPO official languages on 23.05.2002 takes the place of the publication of the European patent application.
[2003/33]
Search report(s)International search report - published on:EP23.05.2002
ClassificationIPC:H01L21/336, H01L21/28, H01L21/265, H01L29/78, H01L29/423, H01L29/10, H01L29/49
[2003/33]
CPC:
H01L29/6659 (EP,US); H01L21/18 (KR); H01L21/26586 (EP,US);
H01L21/2807 (EP,US); H01L21/28114 (EP,US); H01L21/28123 (EP,US);
H01L29/1045 (EP,US); H01L29/42376 (EP,US); H01L29/4966 (EP,US);
H01L29/4991 (EP,US); H01L29/7833 (EP,US) (-)
Designated contracting statesAT,   BE,   CH,   CY,   DE,   DK,   ES,   FI,   FR,   GB,   GR,   IE,   IT,   LI,   LU,   MC,   NL,   PT,   SE,   TR [2003/33]
Extension statesALNot yet paid
LTNot yet paid
LVNot yet paid
MKNot yet paid
RONot yet paid
SINot yet paid
TitleGerman:FELDEFFEKTTRANSISTOR MIT EINER KERBENFÖRMIGEN GATE UND HERSTELLUNGSVERFAHREN[2003/33]
English:FET WITH NOTCHED GATE AND METHOD OF MANUFACTURING THE SAME[2003/33]
French:FET A GRILLE A ENCOCHE ET SON PROCEDE DE FABRICATION[2003/33]
Entry into regional phase30.05.2003National basic fee paid 
30.05.2003Designation fee(s) paid 
30.05.2003Examination fee paid 
Examination procedure05.12.2001Request for preliminary examination filed
International Preliminary Examining Authority: EP
30.05.2003Examination requested  [2003/33]
12.08.2003Loss of particular rights, legal effect: Claims
16.09.2003Despatch of communication of loss of particular rights: Claims {1}
21.11.2008Despatch of a communication from the examining division (Time limit: M04)
11.02.2009Reply to a communication from the examining division
25.03.2009Despatch of a communication from the examining division (Time limit: M04)
28.05.2009Reply to a communication from the examining division
22.09.2009Application withdrawn by applicant  [2009/44]
04.02.2010Date of oral proceedings
Fees paidRenewal fee
07.11.2003Renewal fee patent year 03
22.11.2004Renewal fee patent year 04
22.11.2005Renewal fee patent year 05
17.11.2006Renewal fee patent year 06
16.11.2007Renewal fee patent year 07
17.11.2008Renewal fee patent year 08
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Cited inInternational search[X]JPH10294453  ;
 [A]US5650343  (LUNING SCOTT [US], et al) [A] 1-53 * the whole document *;
 [A]US5650342  (SATOH SHINICHI [JP], et al) [A] 1-53* the whole document *;
 [X]US6037630  (IGARASHI MOTOSHIGE [JP], et al) [X] 1,2,9,10,12,15,16,20,22-26,30,32,36,47,50 * column 7, line 30 - column 9, line 4; figure 9 *;
 [A]FR2791177  (FRANCE TELECOM [FR]) [A] 1-53 * the whole document *;
 [X]  - PATENT ABSTRACTS OF JAPAN, (19990226), vol. 1999, no. 02, & JP10294453 A 19981104 (NEC CORP) [X] 1-6,9,10,12,16-19 * abstract *
 [X]  - SKOTNICKI T ET AL, "WELL-CONTROLLED, SELECTIVELY UNDER-ETCHED SI/SIGE GATES FOR RF AND HIGH PERFORMANCE CMOS", 2000 SYMPOSIUM ON VLSI TECHNOLOGY. DIGEST OF TECHNICAL PAPERS. HONOLULU, JUNE 13-15, 2000, SYMPOSIUM ON VLSI TECHNOLOGY, NEW YORK, NY: IEEE, US, (20000613), ISBN 0-7803-6306-X, pages 156 - 157, XP000970799 [X] 1-6,9,10,12-15,20,22-26,28-30,47-51 * the whole document *
by applicantUS5750430
 FR2791177
    - T. GHANI ET AL., TECHNICAL DIGEST OF THE 1999 INTERNATIONAL ELECTRON DEVICES MEETING, (1999), page 415
The EPO accepts no responsibility for the accuracy of data originating from other authorities; in particular, it does not guarantee that it is complete, up to date or fit for specific purposes.