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EP1298711
European procedure
Extract from the Register of European Patents
EP About this file: EP1298711
| EP1298711 - Manufacturing method of an integrated semiconductor arrangement [Right-click to bookmark this link] | |||
| Former [2003/14] | Manufacturing method of an integrated semiconductor arrangement and semiconductor arrangement thus produced | ||
| [2010/37] | Status | No opposition filed within time limit Status updated on 16.12.2011 Database last updated on 04.06.2024 | Most recent event Tooltip | 16.12.2011 | No opposition filed within time limit | published on 18.01.2012 [2012/03] | Applicant(s) | For all designated states Infineon Technologies AG Am Campeon 1-12 85579 Neubiberg / DE | [2010/22] |
| Former [2003/14] | For all designated states Infineon Technologies AG St.-Martin-Strasse 53 81669 München / DE | Inventor(s) | 01 /
Hammer, Markus Frühlingstrasse 3 93342 Saal a.d. Donau / DE | [2003/14] | Representative(s) | Kindermann, Peter Patentanwälte Kindermann Postfach 10 02 34 85593 Baldham / DE | [N/P] |
| Former [2003/14] | Kindermann, Peter, Dipl.-Ing. Kindermann Patentanwälte Karl-Böhm-Strasse 1 85598 Baldham / DE | Application number, filing date | 02018590.6 | 19.08.2002 | [2003/14] | Priority number, date | DE2001148491 | 01.10.2001 Original published format: DE 10148491 | [2003/14] | Filing language | DE | Procedural language | DE | Publication | Type: | A2 Application without search report | No.: | EP1298711 | Date: | 02.04.2003 | Language: | DE | [2003/14] | Type: | A3 Search report | No.: | EP1298711 | Date: | 19.04.2006 | [2006/16] | Type: | B1 Patent specification | No.: | EP1298711 | Date: | 09.02.2011 | Language: | DE | [2011/06] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 02.03.2006 | Classification | IPC: | H01L21/28, H01L29/788, H01L29/423 | [2006/16] | CPC: |
H01L29/40114 (EP,US);
H01L29/66825 (EP,US)
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| Former IPC [2003/14] | H01L21/28, H01L29/788 | Designated contracting states | FR, IT [2006/52] |
| Former [2003/14] | AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, IE, IT, LI, LU, MC, NL, PT, SE, SK, TR | Title | German: | Verfahren zum Herstellen einer integrierten Halbleiteranordnung | [2010/37] | English: | Manufacturing method of an integrated semiconductor arrangement | [2010/37] | French: | Procédé de fabrication d'un dispositif semi-conducteur intégré | [2010/37] |
| Former [2003/14] | Verfahren zum Herstellen einer integrierten Halbleiteranordnung und zugehörige Halbleiteranordnung | ||
| Former [2003/14] | Manufacturing method of an integrated semiconductor arrangement and semiconductor arrangement thus produced | ||
| Former [2003/14] | Procédé de fabrication d'un dispositif semi-conducteur intégré et dispositif semi-conducteur produit selon ce procédé | Examination procedure | 12.05.2006 | Examination requested [2006/26] | 14.11.2007 | Despatch of a communication from the examining division (Time limit: M04) | 07.03.2008 | Reply to a communication from the examining division | 15.06.2010 | Despatch of a communication from the examining division (Time limit: M02) | 15.07.2010 | Reply to a communication from the examining division | 06.10.2010 | Communication of intention to grant the patent | 16.12.2010 | Fee for grant paid | 16.12.2010 | Fee for publishing/printing paid | Opposition(s) | 10.11.2011 | No opposition filed within time limit [2012/03] | Fees paid | Renewal fee | 24.08.2004 | Renewal fee patent year 03 | 26.08.2005 | Renewal fee patent year 04 | 29.08.2006 | Renewal fee patent year 05 | 14.08.2007 | Renewal fee patent year 06 | 07.08.2008 | Renewal fee patent year 07 | 20.08.2009 | Renewal fee patent year 08 | 17.08.2010 | Renewal fee patent year 09 |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | JPH09205157 [ ]; | [XA]EP0373698 (PHILIPS NV [NL]) [X] 1,3,9-17 * page 4, column 6, line 33 - page 7, column 12, line 49; figures 1a-7b * [A] 2,4-8; | [XA]US5017979 (FUJII TETSUO [JP], et al) [X] 1-4,11-17 * column 3, line 41 - column 5, line 33; figures 1-4 * [A] 5-10; | [YA]US5210044 (YOSHIKAWA KUNIYOSHI [JP]) [Y] 2,4-8 * column 3, line 16 - column 5, line 15; figures 4a-4g * [A] 1; | [XY]US5460991 (HONG GARY [TW]) [X] 1,3,9-17 * the whole document * [Y] 2,4-8; | [XA]JPH09205157 (RICOH KK) [X] 1-8,11-17 * the whole document * [A] 9,10; | [A] - LAI W H ET AL, "Growth characterization of rapid thermal oxides", JOURNAL OF VACUUM SCIENCE & TECHNOLOGY B: MICROELECTRONICS PROCESSING AND PHENOMENA, AMERICAN VACUUM SOCIETY, NEW YORK, NY, US, (199909), vol. 17, no. 5, ISSN 0734-211X, pages 2226 - 2238, XP012007722 [A] 1-17 * the whole document * DOI: http://dx.doi.org/10.1116/1.590898 | [ ] - PATENT ABSTRACTS OF JAPAN, (19971225), vol. 1997, no. 12, & JP09205157 A 19970805 (RICOH CO LTD) [ ] * abstract * | by applicant | EP0373698 | US5210044 | US5460991 | JPH09205157 | - W. H. LAI, U. A., "Growth characterization of rapid thermal oxides", J. VAC. SCI TECHNOL. B, (199909), pages 2226 - 2238 |