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EP1293906
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EP About this file: EP1293906
| EP1293906 - A semiconductor memory device with a large storage capacity memory and a fast speed memory [Right-click to bookmark this link] | Status | The application is deemed to be withdrawn Status updated on 27.08.2005 Database last updated on 17.05.2024 | Most recent event Tooltip | 27.08.2005 | Application deemed to be withdrawn | published on 12.10.2005 [2005/41] | Applicant(s) | For all designated states MITSUBISHI DENKI KABUSHIKI KAISHA 2-3, Marunouchi 2-chome Chiyoda-ku Tokyo / JP | [N/P] |
| Former [2003/12] | For all designated states MITSUBISHI DENKI KABUSHIKI KAISHA 2-3, Marunouchi 2-chome Chiyoda-ku Tokyo / JP | Inventor(s) | 01 /
Konishi, Yasuhiro, Mitsubishi Denki K. K. LSI Kenkyusho, 1 Mizuhara 4-chome Itami-shi, Hyogo-ken / JP | 02 /
Dosaka, Katsumi, Mitsubishi Denki K. K. LSI Kenkyusho, 1 Mizuhara 4-chome Itami-shi, Hyogo-ken / JP | 03 /
Iwamoto, Hisashi, Mitsubishi Denki K. K. LSI Kenkyusho, 1 Mizuhara 4-chome Itami-shi, Hyogo-ken / JP | 04 /
Kumanoya, Masaki, Mitsubishi Denki K. K. LSI Kenkyusho, 1 Mizuhara 4-chome Itami-shi, Hyogo-ken / JP | 05 /
Yamazaki, Akira, Mitsubishi Denki K. K. LSI Kenkyusho, 1 Mizuhara 4-chome Itami-shi, Hyogo-ken / JP | 06 /
Hayano, Kouji, Mitsubishi Denki K. K., Kaisha Kitaitami Seisakusho, 1 Mizuhara 4-chome Itami-shi, Hyogo-ken / JP | [2003/12] | Representative(s) | Beresford, Keith Denis Lewis, et al Beresford Crump LLP 16 High Holborn London WC1V 6BX / GB | [N/P] |
| Former [2003/12] | Beresford, Keith Denis Lewis, et al BERESFORD & Co. 2-5 Warwick Court, High Holborn London WC1R 5DH / GB | Application number, filing date | 02080048.8 | 27.09.1991 | [2003/12] | Priority number, date | JP19900406040 | 25.12.1990 Original published format: JP 40604090 | JP19910017677 | 08.02.1991 Original published format: JP 1767791 | JP19910084248 | 16.04.1991 Original published format: JP 8424891 | [2003/12] | Filing language | EN | Procedural language | EN | Publication | Type: | A2 Application without search report | No.: | EP1293906 | Date: | 19.03.2003 | Language: | EN | [2003/12] | Type: | A3 Search report | No.: | EP1293906 | Date: | 19.05.2004 | [2004/21] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 02.04.2004 | Classification | IPC: | G06F12/08, G11C7/10 | [2003/12] | CPC: |
G11C7/1006 (EP,US);
G11C11/04 (KR);
G06F12/0893 (EP,US);
G11C11/005 (EP,US);
G11C7/103 (EP,US);
G11C7/1045 (EP,US);
G11C2207/2254 (EP,US)
(-)
| Designated contracting states | DE, FR, GB, IT [2003/12] | Title | German: | Halbleiterspeichervorrichtung mit einem grossen Speicher und einem Hochgeschwindigkeitsspeicher | [2003/12] | English: | A semiconductor memory device with a large storage capacity memory and a fast speed memory | [2003/12] | French: | Dispositif de mémoire semi-conductrice avec une mémoire à grande capacité et une mémoire à grande vitesse | [2003/12] | Examination procedure | 20.11.2004 | Application deemed to be withdrawn, date of legal effect [2005/41] | 21.04.2005 | Despatch of communication that the application is deemed to be withdrawn, reason: examination fee not paid in time [2005/41] | Parent application(s) Tooltip | EP00202043.6 / EP1050820 | EP91308902.5 / EP0492776 | EP97202423.6 / EP0811979 | Fees paid | Renewal fee | 20.12.2002 | Renewal fee patent year 03 | 20.12.2002 | Renewal fee patent year 04 | 20.12.2002 | Renewal fee patent year 05 | 20.12.2002 | Renewal fee patent year 06 | 20.12.2002 | Renewal fee patent year 07 | 20.12.2002 | Renewal fee patent year 08 | 20.12.2002 | Renewal fee patent year 09 | 20.12.2002 | Renewal fee patent year 10 | 20.12.2002 | Renewal fee patent year 11 | 20.12.2002 | Renewal fee patent year 12 | 19.09.2003 | Renewal fee patent year 13 | Penalty fee | Penalty fee Rule 85b EPC 1973 | 14.01.2005 | M01 Not yet paid | Additional fee for renewal fee | 30.09.2004 | 14 M06 Not yet paid |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [Y]US4849935 (MIYAZAWA YUICHI [JP]) [Y] 2-5 * abstract ** column 2, line 10 - column 4, line 49; figures 2,3 *; | [XY] - HIDETO HIDAKA ET AL, "THE CACHE DRAM ARCHITECTURE: A DRAM WITH AN ON-CHIP CACHE MEMORY", IEEE MICRO, IEEE INC. NEW YORK, US, (19900401), vol. 10, no. 2, ISSN 0272-1732, pages 14 - 25, XP000116649 [X] 1,8 * page 18, column R, paragraph L - page 19, column L, paragraph 3; figure 4 * [Y] 2-5 |