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Extract from the Register of European Patents

EP About this file: EP1284454

EP1284454 - Method and apparatus for simulation system compiler [Right-click to bookmark this link]
StatusThe application is deemed to be withdrawn
Status updated on  19.08.2005
Database last updated on 15.06.2024
Most recent event   Tooltip11.07.2008Change - representativepublished on 13.08.2008  [2008/33]
Applicant(s)For all designated states
SUN MICROSYSTEMS, INC.
4150 Network Circle
Santa Clara, California 95054 / US
[N/P]
Former [2003/08]For all designated states
Sun Microsystems, Inc.
4150 Network Circle
Santa Clara, California 95054 / US
Inventor(s)01 / Broughton, Jeffrey M.
5441 Hopkins Court
Pleasanton, CA 94566 / US
02 / Chen, Liang T.
13795 Calle Tacuba Drive
Saratoga, CA 95070 / US
03 / Lam, William Kwei-Cheung
5633 Byington Drive
Newark, CA 94560 / US
04 / Pappas, Derek E.
655 Tamarack Drive
Union City, CA 94587 / US
05 / Chen, Ihao
6091 Prince Drive
San Jose, CA 95129 / US
06 / McWilliams, Thomas M.
1350 Sherman Avenue
Menlo Park, CA 94025 / US
07 / Narang, Ankur
1035 D/I Vasant Kunj
110070, New Delhi / IN
08 / Rubin, Jeffrey B.
6361 Paseo Santa Maria
Pleasanton, CA 94566 / US
09 / Cohen, Earl T.
43750 Cameron Hill Drive
Fremont, CA 94539 / US
10 / Parkin, Michael W.
4277 Mackay Drive
Palo Alto, CA 94306 / US
11 / Saulsbury, Ashley N.
18488 Grizzly Rock Road
Los Gatos, CA 95033 / US
12 / Ball, Michael S.
10453 Sierra Vista Lane
La Mesa, CA 91941 / US
 [2003/08]
Representative(s)Harris, Ian Richard, et al
D Young & Co LLP
120 Holborn
London EC1N 2DY / GB
[N/P]
Former [2008/33]Harris, Ian Richard, et al
D Young & Co 120 Holborn
London EC1N 2DY / GB
Former [2008/28]Harris, Ian Richard, et al
D Young & Co 120 Holborn
London EC1N 2DY / GB
Former [2003/08]Weihs, Bruno
Rosenthal & Osha S.A.R.L. 121, avenue des Champs Elysées
75008 Paris / FR
Application number, filing date02102115.908.08.2002
[2003/08]
Priority number, dateUS20010313217P17.08.2001         Original published format: US 313217 P
US20010313762P20.08.2001         Original published format: US 313762 P
US2002011358229.03.2002         Original published format: US 113582
[2003/08]
Filing languageEN
Procedural languageEN
PublicationType: A2 Application without search report 
No.:EP1284454
Date:19.02.2003
Language:EN
[2003/08]
Type: A3 Search report 
No.:EP1284454
Date:08.09.2004
[2004/37]
Search report(s)(Supplementary) European search report - dispatched on:EP19.07.2004
ClassificationIPC:G06F9/45, G06F17/50
[2004/22]
CPC:
G06F8/427 (EP,US); G06F30/33 (EP,US); G06F8/443 (EP,US);
G06F8/445 (EP,US); G06F8/45 (EP,US)
Former IPC [2003/08]G06F9/45
Designated contracting states(deleted) [2005/21]
Former [2003/08]AT,  BE,  BG,  CH,  CY,  CZ,  DE,  DK,  EE,  ES,  FI,  FR,  GB,  GR,  IE,  IT,  LI,  LU,  MC,  NL,  PT,  SE,  SK,  TR 
TitleGerman:Verfahren und Gerät für einen Simulationssystemkompiler[2003/08]
English:Method and apparatus for simulation system compiler[2003/08]
French:Méthode et appareil pour compilateur de système de simulation[2003/08]
Examination procedure01.03.2005Application deemed to be withdrawn, date of legal effect  [2005/40]
18.04.2005Despatch of communication that the application is deemed to be withdrawn, reason: renewal fee not paid in time  [2005/40]
Fees paidPenalty fee
Additional fee for renewal fee
31.08.200403   M06   Not yet paid
Opt-out from the exclusive  Tooltip
competence of the Unified
Patent Court		 See the Register of the Unified Patent Court for opt-out data
Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court.
Documents cited:Search[X]US5274818  (VASILEVSKY ALEXANDER D [US], et al) [X] 1,3-11,13-21,25,27,29,36-42,44-54,56,57,60,63 * abstract * * column 16, line 56 - column 18, line 31 * * column 18, line 49 - column 25, line 4 * * figures 2,3,11-13 *;
 [A]EP0829812  (SHARP KK [JP]);
 [Y]US6058492  (SAMPLE STEPHEN P [US], et al) [Y] 2-10,12,30,43 * abstract * * column 2, line 36 - line 52 * * column 12, line 39 - line 57 * * column 14, line 4 - line 23 * * figures 1,2,13 *;
 [A]WO0042535  (CHAN TERENCE [US]) [A] 1,3-21,25,27-29,32,36-54,56,57,60,63 * abstract * * page 1, paragraph 4 * * page 3, line 18 - line 31 * * page 8, line 46 - page 9, line 10 * * page 10, line 45 - page 11, line 18 * * figures 1,2,4,5,10 *;
 [XY]EP1107116  (FRONTIER DESIGN BVBA [BE]) [X] 1,11,19,20,25,27-29,36-42,44-47,54,56,57,60,63 * abstract * * paragraph [0001] - paragraph [0004] * * paragraph [0012] * * paragraph [0021] * * page 5, line 3 - line 5 * * paragraph [0025] - paragraph [0029] * * paragraph [0031] - paragraph [0036] * * paragraph [0040] * * figures 1,2,4,7 * [Y] 2-10,12,30,43;
 [X]  - WILLIS J C ET AL, "OPTIMIZING VHDL COMPILATION FOR PARALLEL SIMULATION", IEEE DESIGN & TEST OF COMPUTERS, IEEE COMPUTERS SOCIETY. LOS ALAMITOS, US, (19920901), vol. 9, no. 3, ISSN 0740-7475, pages 42 - 53, XP000306605 [X] 1,36,60,63 * page 42, column M, line 2 - column R, line 16 * * page 42, column R, line 29 - page 43, column L, line 3 * * page 43, column L, line 19 - column R, line 19 * * figure 1 *

DOI:   http://dx.doi.org/10.1109/54.156157
 [A]  - WILLIS J ET AL, "Use of embedded scheduling to compile VHDL for effective parallel simulation", DESIGN AUTOMATION CONFERENCE, 1995, WITH EURO-VHDL, PROCEEDINGS EURO-DAC '95., EUROPEAN BRIGHTON, UK 18-22 SEPT. 1995, LOS ALAMITOS, CA, USA,IEEE COMPUT. SOC, US, (19950918), ISBN 0-8186-7156-4, pages 400 - 405, XP010192944 [A] 1,36,60,63 * abstract * * page 400, column L, line 1 - column R, line 23 * * page 401, column L, line 40 - column R, line 45 *

DOI:   http://dx.doi.org/10.1109/EURDAC.1995.527436
 [A]  - AJLUNI C, "ADVANCED EMULATION TOOL TARGETS HIGH-SPEED FUNCTIONAL VERIFICATION", ELECTRONIC DESIGN, PENTON PUBLISHING, CLEVELAND, OH, US, (19970303), vol. 45, no. 5, ISSN 0013-4872, page 80,82, XP001172984 [A] 1-12 * the whole document *
The EPO accepts no responsibility for the accuracy of data originating from other authorities; in particular, it does not guarantee that it is complete, up to date or fit for specific purposes.