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EP1416388
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EP About this file: EP1416388
| EP1416388 - INTEGRATED CIRCUIT DEVICE [Right-click to bookmark this link] | Status | The application is deemed to be withdrawn Status updated on 18.07.2008 Database last updated on 24.04.2024 | Most recent event Tooltip | 18.07.2008 | Application deemed to be withdrawn | published on 20.08.2008 [2008/34] | Applicant(s) | For all designated states IP Flex Inc. 27-1, Kamiosaki 2-chome, Shinagawa-ku Tokyo 141-0021 / JP | [N/P] |
| Former [2004/19] | For all designated states IP Flex Inc. 27-1, Kamiosaki 2-chome, Shinagawa-ku Tokyo 141-0021 / JP | Inventor(s) | 01 /
IKEDA, Kenji B, Sunny Home, 1-12-12, Koyamadai, Shinagawa-ku Tokyo 142-0061 / JP | [2004/19] | Representative(s) | Körber, Martin Hans Mitscherlich PartmbB Patent- und Rechtsanwälte Postfach 33 06 09 80066 München / DE | [N/P] |
| Former [2004/19] | Körber, Martin, Dipl.-Phys. Mitscherlich & Partner Patentanwälte Sonnenstrasse 33 80331 München / DE | Application number, filing date | 02745985.8 | 11.07.2002 | [2004/19] | WO2002JP07076 | Priority number, date | JP20010212545 | 12.07.2001 Original published format: JP 2001212545 | [2004/19] | Filing language | JA | Procedural language | EN | Publication | Type: | A1 Application with search report | No.: | WO03007155 | Date: | 23.01.2003 | Language: | EN | [2003/04] | Type: | A1 Application with search report | No.: | EP1416388 | Date: | 06.05.2004 | Language: | EN | The application published by WIPO in one of the EPO official languages on 23.01.2003 takes the place of the publication of the European patent application. | [2004/19] | Search report(s) | International search report - published on: | JP | 23.01.2003 | (Supplementary) European search report - dispatched on: | EP | 22.12.2005 | Classification | IPC: | G06F12/08, G06F15/16, G06F15/78 | [2004/19] | CPC: |
G06F15/7867 (EP,US);
G06F3/00 (KR);
G06F15/781 (EP,US)
| Designated contracting states | AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, IE, IT, LI, LU, MC, NL, PT, SE, SK, TR [2004/19] | Title | German: | INTEGRIERTES SCHALTUNGSBAUELEMENT | [2004/19] | English: | INTEGRATED CIRCUIT DEVICE | [2004/19] | French: | DISPOSITIF A CIRCUIT INTEGRE | [2004/19] | Entry into regional phase | 09.12.2003 | Translation filed | 09.12.2003 | National basic fee paid | 09.12.2003 | Search fee paid | 09.12.2003 | Designation fee(s) paid | 09.12.2003 | Examination fee paid | Examination procedure | 31.01.2003 | Request for preliminary examination filed International Preliminary Examining Authority: JP | 09.12.2003 | Examination requested [2004/19] | 12.01.2007 | Despatch of a communication from the examining division (Time limit: M06) | 09.07.2007 | Reply to a communication from the examining division | 12.10.2007 | Despatch of a communication from the examining division (Time limit: M04) | 23.02.2008 | Application deemed to be withdrawn, date of legal effect [2008/34] | 02.04.2008 | Despatch of communication that the application is deemed to be withdrawn, reason: reply to the communication from the examining division not received in time [2008/34] | Fees paid | Renewal fee | 30.07.2004 | Renewal fee patent year 03 | 29.07.2005 | Renewal fee patent year 04 | 28.07.2006 | Renewal fee patent year 05 | 30.07.2007 | Renewal fee patent year 06 |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [A]US5968160 (SAITO MASAHIKO [JP], et al) [A] 1-40* the whole document *; | [XA] - RUPP C R ET AL, "The NAPA adaptive processing architecture", FPGAS FOR CUSTOM COMPUTING MACHINES, 1998. PROCEEDINGS. IEEE SYMPOSIUM ON NAPA VALLEY, CA, USA 15-17 APRIL 1998, LOS ALAMITOS, CA, USA,IEEE COMPUT. SOC, US, (19980415), ISBN 0-8186-8900-5, pages 28 - 37, XP010298175 [X] 1-6,9,14-19,21,22,25,28,29,31-35,37 * page 32, column L, line 1 - line 40 * * page 33, column R, line 11 - line 40 * * page 32, column L, line 43 - column R, line 1 * * figures 2,4 * [A] 7,8,10-13,20,23,24,26,27,30,36,38-40 DOI: http://dx.doi.org/10.1109/FPGA.1998.707878 | [XA] - R.W HARTENSTEIN, A.G HIRSCHBEL, M WEBER, "The Machine Paradigm of XPuters : and its Application to Digital Signal Processing Acceleration", INT. WORKSHOP ON ALGORITHMS AND PARALLEL VLSI ARCHITECTURES, Pont-y-Mousson, France, (1990), URL: http://xputers.informatik.uni-kl.de/papers/paper024.pdf, (20051206), XP002357487 [X] 1,2,4,5,12,14-21,28,30-36,38 * the whole document * * figure 1b * * figure 5c * * figure 2a * * figure 7a * * figure 12 * * figure 12a * * figure 12c * [A] 3,6-11,13,22-27,29,37,39,40 | International search | [Y]JPS649548 (NEC CORP); | [Y]JPH01273132 (NEC CORP); | [Y]JPH11143774 (HITACHI LTD); | [YE]JP2002163150 (TOSHIBA CORP); | [AE] - COMPTON K., "Reconfigurable computing: A survey of systems and software", ACM COMPUTING SURVEYS, (200206), vol. 34, no. 2, page 171 AND 210, XP002957662 DOI: http://dx.doi.org/10.1145/508352.508353 | [A] - KIM H.S. ET AL., "A reconfigurable multi-function computing cache architecture", PROCEEDINGS OF ACM/SIGDA INTERNATIONAL SYMPOSIUM ON FIELD PROGRAMMABLE GATE ARRAYS, (2000), page 85 AND 94, XP000970735 DOI: http://dx.doi.org/10.1145/329166.329185 | [A] - RANGANATHAN P. ET AL., "Reconfigurable caches and their application to media processing", PROCEEDINGS OF THE 27TH INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE (ISCA 27), (200006), page 214 AND 224, XP000928730 DOI: http://dx.doi.org/10.1145/342001.339685 |