EP1530761 - VERTICAL INSTRUCTION AND DATA PROCESSING IN A NETWORK PROCESSOR ARCHITECTURE [Right-click to bookmark this link] | Status | The application has been withdrawn Status updated on 16.10.2009 Database last updated on 02.07.2024 | Most recent event Tooltip | 16.10.2009 | Withdrawal of application | published on 18.11.2009 [2009/47] | Applicant(s) | For all designated states Bay Microsystems, Inc. Suite 298, 2700 Augustine Drive Santa Clara, CA 95054 / US | [2005/20] | Inventor(s) | 01 /
LEE, Barry 4911 Antioch Street Union City, CA 94587 / US | 02 /
ONO, Golchiro 4923 Palacewood Court San Jose, CA 95129 / US | 03 /
TRINH, Man, Dieu 2215 Emerald Hills Drive San Jose, CA 95131 / US | 04 /
BLESZYNSKI, Ryszard 18817 Bellgrove Circle Saratoga, CA 95070 / US | [2005/20] | Representative(s) | Vleck, Jan Montagu Reddie & Grose LLP The White Chapel Building 10 Whitechapel High Street London E1 8QS / GB | [N/P] |
Former [2005/20] | Vleck, Jan Montagu Reddie & Grose, 16 Theobalds Road London WC1X 8PL / GB | Application number, filing date | 02761755.4 | 19.09.2002 | [2005/20] | WO2002US29907 | Priority number, date | US20010323627P | 19.09.2001 Original published format: US 323627 P | US20020372507P | 14.04.2002 Original published format: US 372507 P | US20020382437P | 20.05.2002 Original published format: US 382437 P | [2005/20] | Filing language | EN | Procedural language | EN | Publication | Type: | A2 Application without search report | No.: | WO03025709 | Date: | 27.03.2003 | Language: | EN | [2003/13] | Type: | A2 Application without search report | No.: | EP1530761 | Date: | 18.05.2005 | Language: | EN | The application published by WIPO in one of the EPO official languages on 27.03.2003 takes the place of the publication of the European patent application. | [2005/20] | Search report(s) | International search report - published on: | US | 17.03.2005 | (Supplementary) European search report - dispatched on: | EP | 02.01.2008 | Classification | IPC: | G06F15/00 | [2005/20] | CPC: |
G06F9/3885 (EP);
H04L47/22 (US);
G06F15/00 (EP);
G06F17/00 (US);
H04L12/28 (EP);
H04L12/56 (EP);
| Designated contracting states | AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, IE, IT, LI, LU, MC, NL, PT, SE, SK, TR [2005/20] | Title | German: | VERTIKAL-ANWEISUNGS- UND DATENVERARBEITUNG IN EINER NETZWERKPROZESSORARCHITEKTUR | [2005/20] | English: | VERTICAL INSTRUCTION AND DATA PROCESSING IN A NETWORK PROCESSOR ARCHITECTURE | [2005/20] | French: | TRAITEMENT VERTICAL D'INSTRUCTIONS ET DE DONNEES DANS UNE ARCHITECTURE DE PROCESSEUR EN RESEAU | [2005/20] | Entry into regional phase | 07.04.2004 | National basic fee paid | 07.04.2004 | Search fee paid | 07.04.2004 | Designation fee(s) paid | 07.04.2004 | Examination fee paid | Examination procedure | 11.04.2003 | Request for preliminary examination filed International Preliminary Examining Authority: US | 07.04.2004 | Examination requested [2005/20] | 17.05.2005 | Amendment by applicant (claims and/or description) | 25.06.2008 | Despatch of a communication from the examining division (Time limit: M06) | 03.12.2008 | Reply to a communication from the examining division | 09.04.2009 | Despatch of a communication from the examining division (Time limit: M06) | 08.10.2009 | Application withdrawn by applicant [2009/47] | Fees paid | Renewal fee | 07.04.2004 | Renewal fee patent year 03 | 29.09.2005 | Renewal fee patent year 04 | 20.09.2006 | Renewal fee patent year 05 | 24.09.2007 | Renewal fee patent year 06 | 14.10.2008 | Renewal fee patent year 07 | Penalty fee | Additional fee for renewal fee | 30.09.2008 | 07   M06   Fee paid on   14.10.2008 |
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Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [Y]EP0432924 (AMERICAN TELEPHONE & TELEGRAPH [US]) [Y] 1-6 * abstract * * column 6, line 53 - column 10, line 23 *; | [A]US5423051 (FULLER RICHARD A [US], et al) [A] 1-6 * column 11, line 1 - column 12, line 16; figures 5,6 *; | [Y]WO0116702 (INTEL CORP [US], et al) [Y] 1-6 * page 10, line 15 - line 28 *; | [A] - PYEONG JUNG KIM ET AL, "Horizontal architecture for high performance parallel communication systems", INSPEC, THE INSTITUTION OF ELECTRICAL ENGINEERS, STEVENAGE, GB, (1997), Database accession no. 5577953, XP002457737 [A] 1-6 * abstract * * paragraphs [0003] - [0005] * | [A] - CHOI S ET AL, "IMPLEMENTING OSI PROTOCOL STACK IN A MULTIPROCESSOR ENVIRONMENT", IEICE TRANSACTIONS ON COMMUNICATIONS, COMMUNICATIONS SOCIETY, TOKYO, JP, (199601), vol. E79-B, no. 1, ISSN 0916-8516, pages 28 - 36, XP000556190 [A] 1-6 * abstract * * paragraph [0004] * | [A] - SCHOLZ T ET AL, "An improved dynamic register array concept for high-performance RISC processors", INSPEC, THE INSTITUTION OF ELECTRICAL ENGINEERS, STEVENAGE, GB, (1995), Database accession no. 4869901, XP002457738 [A] 1-6 * abstract * * paragraphs [0002] - [0004] * | [A] - PROCEEDINGS HIGH PERFORMANCE COMPUTING ON THE INFORMATION SUPERHIGHWAY. HPC ASIA '97 28 APRIL-2 MAY 1997 SEOUL, SOUTH KOREA, Proceedings. High Performance Computing on the Information Superhighway HPC Asia '97 (Cat. No.97TB100110) IEEE Comput. Soc. Press Los Alamitos, CA, USA, (1997), ISBN 0-8186-7901-8, pages 472 - 477 [A] 1-6 | [ ] - PROCEEDINGS OF THE TWENTY-EIGHTH ANNUAL HAWAII INTERNATIONAL CONFERENCE ON SYSTEM SCIENCES 3-6 JAN. 1995 WAILEA, HI, USA, Proceedings of the Twenty-Eighth Hawaii International Conference on System Sciences IEEE Comput. Soc. Press Los Alamitos, CA, USA, (1995), vol. 1, ISBN 0-8186-6930-6, pages 181 - 190 vol.1 | International search | [AP]US6367005 (ZAHIR ACHMED RUMI [US], et al); | [AP]US2002056037 (WOLRICH GILBERT [US], et al); | [XP]US6421730 (NARAD CHARLES E [US], et al); | [YE]US2002163905 (BRABRAND TORD [NO]); | [YE]US2002181455 (NORMAN RICHARD S [CA], et al); | [XE]US6668317 (BERNSTEIN DEBRA [US], et al); | [YE]US6721271 (BESHAI MAGED E [CA], et al); | [YE]US6807193 (BESER NURETTIN B [US]) |