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EP1432033
European procedure
Extract from the Register of European Patents
EP About this file: EP1432033
| EP1432033 - Multi-chip module and method of forming [Right-click to bookmark this link] | Status | No opposition filed within time limit Status updated on 07.09.2007 Database last updated on 04.06.2024 | Most recent event Tooltip | 07.09.2007 | No opposition filed within time limit | published on 10.10.2007 [2007/41] | Applicant(s) | For all designated states Delphi Technologies, Inc. PO Box 5052 Troy, MI 48007 / US | [2004/26] | Inventor(s) | 01 /
Brandenburg, Scott D. 4003 Hermitage Lane Kokomo, Indiana 46902 / US | [2004/26] | Representative(s) | Denton, Michael John Delphi France SAS Bât. le Raspail - ZAC Paris Nord 2 22, avenue des Nations CS 65059 Villepinte 95972 Roissy CDG Cedex / FR | [N/P] |
| Former [2004/26] | Denton, Michael John Delphi European Headquarters, 64 avenue de la Plaine de France, Paris Nord II, BP 60059, Tremblay-en-France 95972 Roissy Charles de Gaulle Cédex / FR | Application number, filing date | 03078782.4 | 28.11.2003 | [2004/26] | Priority number, date | US20020321900 | 17.12.2002 Original published format: US 321900 | [2004/26] | Filing language | EN | Procedural language | EN | Publication | Type: | A1 Application with search report | No.: | EP1432033 | Date: | 23.06.2004 | Language: | EN | [2004/26] | Type: | B1 Patent specification | No.: | EP1432033 | Date: | 02.11.2006 | Language: | EN | [2006/44] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 03.03.2004 | Classification | IPC: | H01L25/065, H01L23/10, H01L21/56 | [2004/26] | CPC: |
H01L23/3128 (EP,US);
H01L21/56 (EP,US);
H01L23/5385 (EP,US);
H01L2224/48227 (EP,US);
H01L2224/73204 (EP,US);
H01L24/48 (EP,US);
H01L25/0652 (EP,US);
H01L2924/00014 (EP,US);
H01L2924/00015 (EP,US);
| C-Set: |
H01L2924/00014, H01L2224/45015, H01L2924/207 (EP,US);
H01L2924/00014, H01L2224/45099 (EP,US);
H01L2924/00015, H01L2224/05599 (US,EP);
H01L2924/00015, H01L2224/45099 (US,EP);
H01L2924/00015, H01L2224/85399 (US,EP);
H01L2924/14, H01L2924/00 (US,EP); | Designated contracting states | DE, FR, GB [2005/11] |
| Former [2004/26] | AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HU, IE, IT, LI, LU, MC, NL, PT, RO, SE, SI, SK, TR | Title | German: | Multichip-modul und Herstellungsverfahren | [2004/26] | English: | Multi-chip module and method of forming | [2004/26] | French: | Module multi-puce et méthode de fabrication | [2004/26] | Examination procedure | 23.12.2004 | Examination requested [2005/08] | 03.02.2005 | Despatch of a communication from the examining division (Time limit: M04) | 08.04.2005 | Reply to a communication from the examining division | 22.09.2005 | Despatch of a communication from the examining division (Time limit: M04) | 07.10.2005 | Reply to a communication from the examining division | 08.05.2006 | Communication of intention to grant the patent | 18.09.2006 | Fee for grant paid | 18.09.2006 | Fee for publishing/printing paid | Opposition(s) | 03.08.2007 | No opposition filed within time limit [2007/41] | Fees paid | Renewal fee | 30.11.2005 | Renewal fee patent year 03 |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [Y]US5448825 (LEE SANG S [US], et al) [Y] 18 * figure 4 *; | [XY]US5570274 (SAITO MASARU [JP], et al) [X] 1-4,8,9,11-14,19 * column 7, line 1 - column 8, line 14; figure 7 * [Y] 5-7,10,15-18,20; | [X]US5615089 (YONEDA YOSHIHIRO [JP], et al) [X] 1,4,8,9,11,14,19 * column 4, line 17 - line 35; figure 3 *; | [A]US5981312 (FARQUHAR DONALD SETON [US], et al) [A] 10,20 * figure 7 *; | [Y]EP1096567 (OKI ELECTRIC IND CO LTD [JP]) [Y] 10,20 * figures 15A-E *; | [Y]US2001013640 (TAO TETSUYA [JP]) [Y] 5-7,15-17 * paragraphs [0040] - [0043] - [0049]; figures 1-4 *; | [A]US6285559 (FUKIHARU EIICHI [JP]) [A] 1-20* figures 3,11,13,15 * |