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EP1406241
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EP About this file: EP1406241
| EP1406241 - Driving circuit and voltage generating circuit and display using the same [Right-click to bookmark this link] | Status | The application has been refused Status updated on 23.10.2015 Database last updated on 23.04.2024 | Most recent event Tooltip | 23.10.2015 | Refusal of application | published on 25.11.2015 [2015/48] | Applicant(s) | For all designated states Gold Charm Limited Offshore Chambers P.O.Box 217 Apia / WS | [2013/08] |
| Former [2004/15] | For all designated states NEC CORPORATION 7-1, Shiba 5-chome, Minato-ku Tokyo / JP | Inventor(s) | 01 /
Abe, Katsumi NEC Corporation, 7-1, Shiba 5-chome Minato-ku, Tokyo / JP | [2004/15] | Representative(s) | Huang, Chongguang, et al CMS Cameron McKenna Nabarro Olswang LLP Cannon Place 78 Cannon Street London EC4N 6AF / GB | [N/P] |
| Former [2013/08] | Gray, John James, et al Murgitroyd & Company Scotland House 165-169 Scotland Street Glasgow G5 8PL / GB | ||
| Former [2012/07] | Stork Bamberger Patentanwälte Postfach 73 04 66 22124 Hamburg / DE | ||
| Former [2004/15] | Patentanwälte Wenzel & Kalkoff Grubesallee 26 22143 Hamburg / DE | Application number, filing date | 03090314.0 | 24.09.2003 | [2004/15] | Priority number, date | JP20020278274 | 25.09.2002 Original published format: JP 2002278274 | [2004/15] | Filing language | EN | Procedural language | EN | Publication | Type: | A2 Application without search report | No.: | EP1406241 | Date: | 07.04.2004 | Language: | EN | [2004/15] | Type: | A3 Search report | No.: | EP1406241 | Date: | 12.03.2008 | [2008/11] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 08.02.2008 | Classification | IPC: | G09G3/36 | [2004/15] | CPC: |
G09G3/3696 (EP,US);
G09G3/3648 (EP,US);
G09G2300/08 (EP,US);
G09G2320/02 (EP,US);
G09G2320/0223 (EP,US);
G09G3/3614 (EP,US)
| Designated contracting states | AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HU, IE, IT, LI, LU, MC, NL, PT, RO, SE, SI, SK, TR [2004/15] | Title | German: | Treiberschaltung und Spannungserzeugungsschaltung sowie Verwendung in einem Anzeigegerät | [2004/15] | English: | Driving circuit and voltage generating circuit and display using the same | [2004/15] | French: | Circuit d'attaque et circuit de génération de tensions et dispositif d'affichage utilisant ces circuits | [2004/15] | Examination procedure | 27.03.2008 | Examination requested [2008/20] | 24.06.2008 | Despatch of a communication from the examining division (Time limit: M04) | 04.11.2008 | Reply to a communication from the examining division | 17.07.2009 | Despatch of a communication from the examining division (Time limit: M06) | 27.01.2010 | Reply to a communication from the examining division | 08.10.2010 | Application refused, date of legal effect [2015/48] | 08.10.2010 | Date of oral proceedings | 30.11.2010 | Despatch of communication that the application is refused, reason: substantive examination [2015/48] | 30.11.2010 | Minutes of oral proceedings despatched | Appeal following examination | 28.01.2011 | Appeal received No. T0949/11 | 08.04.2011 | Statement of grounds filed | 17.09.2015 | Result of appeal procedure: appeal of the applicant was rejected | 17.09.2015 | Date of oral proceedings | 25.09.2015 | Minutes of oral proceedings despatched | Divisional application(s) | EP10075195.7 / EP2219175 | The date of the Examining Division's first communication in respect of the earliest application for which a communication has been issued is 24.06.2008 | Fees paid | Renewal fee | 26.08.2005 | Renewal fee patent year 03 | 28.09.2006 | Renewal fee patent year 04 | 27.09.2007 | Renewal fee patent year 05 | 29.03.2008 | Renewal fee patent year 06 | 26.09.2009 | Renewal fee patent year 07 | 29.09.2010 | Renewal fee patent year 08 | 29.09.2011 | Renewal fee patent year 09 | 27.09.2012 | Renewal fee patent year 10 | 09.09.2013 | Renewal fee patent year 11 | 29.09.2014 | Renewal fee patent year 12 | 25.09.2015 | Renewal fee patent year 13 |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [A]EP0772067 (SEIKO EPSON CORP [JP]) [A] 8-12,20-22 * figure 13 * * column 20, line 1 - line 31 *; | [XA]US2002008686 (KUMADA KOUJI [JP], et al) [X] 8-11,20,21 * paragraph [0067] * * paragraph [0119] - paragraph [0125] * * figure 6 * * figure 3 * [A] 3,15; | [X]US2002018059 (YANAGI TOSHIHIRO [JP], et al) [X] 1-7,14-18 * paragraph [0272] - paragraph [0281] * * figure 10 * * paragraph [0004] *; | [A]EP1195741 (SHARP KK [JP]) [A] 1-12,14-18,20-22 * figure 1 ** paragraph [0021] - paragraph [0049] *; | [XA]JP2002174823 (SONY CORP) [X] 13,19 * abstract * * figure 1 * * figure 3 * * figure 1 * * figure 3 * [A] 2,6,10-12,14-18,20-22 | Examination | - MIKAMI Y. ET AL, "A 5-in. SVGA TFT-LCD with Integrated Multiple DAC Using Low-Temperature poly-Si TFTs", IDW, DE2/AMD1-4, LONDON UK, (20010101), pages 1607 - 1610, XP007015597 | - NAKAMURA TAKASHI ET AL, "Low Temperature Poly-Si TFT-LCD with Integrated Analog Circuit", IDW, DE2/AMD1-3, LONDON UK, (20010101), pages 1603 - 1606, XP007015596 | by applicant | JPH11194320 | JPH11194316 | US2002008686 | US2002018059 | JP2002174823 |