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Extract from the Register of European Patents

EP About this file: EP1545131

EP1545131 - Semiconductor circuit for restricting data access [Right-click to bookmark this link]
StatusNo opposition filed within time limit
Status updated on  23.05.2008
Database last updated on 27.07.2024
Most recent event   Tooltip18.02.2011Lapse of the patent in a contracting state
New state(s): IT
published on 23.03.2011  [2011/12]
Applicant(s)For all designated states
STMicroelectronics Limited
1000 Aztec West Almondsbury
Bristol, BS32 4SQ / GB
[2007/29]
Former [2005/25]For all designated states
STMicroelectronics Limited
1000 Aztec West
Almondsbury, Bristol, BS32 4SQ / GB
Inventor(s)01 / Dellow, Andrew
14 Tetbury Street
Minchinhampton Glouchester GL6 9JG / GB
02 / Cordero, Rodrigo
26 Malborough Street
Eastville Bristol BS5 6RH / GB
 [2005/25]
Representative(s)Loveless, Ian Mark
Reddie & Grose LLP The White Chapel Building
10 Whitechapel High Street
London E1 8QS / GB
[N/P]
Former [2005/25]Loveless, Ian Mark
Reddie & Grose, 16 Theobalds Road
London WC1X 8PL / GB
Application number, filing date03258058.119.12.2003
[2005/25]
Filing languageEN
Procedural languageEN
PublicationType: A1 Application with search report 
No.:EP1545131
Date:22.06.2005
Language:EN
[2005/25]
Type: B1 Patent specification 
No.:EP1545131
Date:18.07.2007
Language:EN
[2007/29]
Search report(s)(Supplementary) European search report - dispatched on:EP16.06.2004
ClassificationIPC:H04N7/167, G06F12/14
[2005/25]
CPC:
H04N21/4181 (EP,US); G06F21/85 (EP,US); H04N21/454 (EP,US);
H04N7/162 (EP,US)
Designated contracting statesDE,   FR,   GB,   IT [2006/11]
Former [2005/25]AT,  BE,  BG,  CH,  CY,  CZ,  DE,  DK,  EE,  ES,  FI,  FR,  GB,  GR,  HU,  IE,  IT,  LI,  LU,  MC,  NL,  PT,  RO,  SE,  SI,  SK,  TR 
TitleGerman:Halbleiterschaltung zur Begrenzung von Datenzugang[2005/25]
English:Semiconductor circuit for restricting data access[2005/25]
French:Circuit à semiconducteur pour restreindre l'accès aux données[2005/25]
Examination procedure21.09.2004Amendment by applicant (claims and/or description)
19.12.2005Examination requested  [2006/07]
26.01.2007Communication of intention to grant the patent
04.06.2007Fee for grant paid
04.06.2007Fee for publishing/printing paid
Opposition(s)21.04.2008No opposition filed within time limit [2008/26]
Fees paidRenewal fee
15.12.2005Renewal fee patent year 03
27.12.2006Renewal fee patent year 04
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Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court.
Lapses during opposition  TooltipDE19.10.2007
IT31.12.2007
[2011/12]
Former [2008/36]DE19.10.2007
Documents cited:Search[A]WO9847060  (DALLAS SEMICONDUCTOR [US]) [A] 1-28 * abstract * * page 3, line 20 - page 4, line 30 * * page 18, line 22 *;
 [Y]EP1043729  (SONY CORP [JP]) [Y] 1-15,17-28 * abstract * * column 21, line 31 - column 22, line 6 *;
 [A]US6553496  (BUER MARK LEONARD [US]) [A] 1-28* abstract *;
 [Y]US2003105976  (COPELAND JOHN A [US]) [Y] 1-15,17-28 * abstract * * paragraph [0015] * * paragraph [0027] * * paragraph [0043] - paragraph [0044] * * paragraph [0089] *;
 [A]US6637027  (BRESLAUER HEIDI H [US], et al) [A] 1-28 * abstract *;
 [A]EP1370084  (ATI TECHNOLOGIES INC [CA]) [A] 1-28 * abstract *
The EPO accepts no responsibility for the accuracy of data originating from other authorities; in particular, it does not guarantee that it is complete, up to date or fit for specific purposes.