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Extract from the Register of European Patents

EP About this file: EP1497861

EP1497861 - SEMICONDUCTOR COMPONENT HAVING AN INTEGRATED CAPACITANCE STRUCTURE AND METHOD FOR PRODUCING THE SAME [Right-click to bookmark this link]
StatusNo opposition filed within time limit
Status updated on  21.03.2008
Database last updated on 05.07.2024
Most recent event   Tooltip21.03.2008No opposition filed within time limitpublished on 23.04.2008  [2008/17]
Applicant(s)For all designated states
Infineon Technologies AG
St.-Martin-Strasse 53
81669 München / DE
[2007/20]
Former [2005/03]For all designated states
Infineon Technologies AG
St.-Martin-Strasse 53
81669 München / DE
Inventor(s)01 / BENETIK, Thomas
Thalkirchner Str.7
80337 München / DE
02 / RUDERER, Erwin
Böhmerwaldstr. 31
85570 Markt Schwaben / DE
 [2005/03]
Representative(s)Graf Lambsdorff, Matthias
Patentanwälte
Lambsdorff & Lange
Dingolfinger Strasse 6
81673 München / DE
[N/P]
Former [2005/03]Graf Lambsdorff, Matthias, Dr.
Patentanwälte Lambsdorff & Lange Dingolfinger Strasse 6
81673 München / DE
Application number, filing date03724840.824.03.2003
[2005/03]
WO2003DE00964
Priority number, dateDE200211756719.04.2002         Original published format: DE 10217567
[2005/03]
Filing languageDE
Procedural languageDE
PublicationType: A1 Application with search report
No.:WO03090280
Date:30.10.2003
Language:DE
[2003/44]
Type: A1 Application with search report 
No.:EP1497861
Date:19.01.2005
Language:DE
The application published by WIPO in one of the EPO official languages on 30.10.2003 takes the place of the publication of the European patent application.
[2005/03]
Type: B1 Patent specification 
No.:EP1497861
Date:16.05.2007
Language:DE
[2007/20]
Search report(s)International search report - published on:EP30.10.2003
ClassificationIPC:H01L23/522
[2005/03]
CPC:
H01L23/5222 (EP,US); H01L28/90 (EP,US); H01L2924/0002 (EP,US)
C-Set:
H01L2924/0002, H01L2924/00 (EP,US)
Designated contracting statesDE,   FR,   GB [2007/20]
Former [2005/03]DE,  FR,  GB,  IT 
TitleGerman:HALBLEITERBAUELEMENT MIT INTEGRIERTER KAPAZITÄTSSTRUKTUR UND VERFAHREN ZU DESSENHERSTELLUNG[2005/03]
English:SEMICONDUCTOR COMPONENT HAVING AN INTEGRATED CAPACITANCE STRUCTURE AND METHOD FOR PRODUCING THE SAME[2005/03]
French:COMPOSANT A SEMI-CONDUCTEUR A STRUCTURE DE CAPACITE INTEGREE ET PROCEDE PERMETTANT DE LE PRODUIRE[2005/03]
Entry into regional phase06.10.2004National basic fee paid 
06.10.2004Designation fee(s) paid 
06.10.2004Examination fee paid 
Examination procedure20.10.2003Request for preliminary examination filed
International Preliminary Examining Authority: EP
06.10.2004Amendment by applicant (claims and/or description)
06.10.2004Examination requested  [2005/03]
11.07.2006Despatch of a communication from the examining division (Time limit: M04)
09.08.2006Reply to a communication from the examining division
10.11.2006Communication of intention to grant the patent
08.03.2007Fee for grant paid
08.03.2007Fee for publishing/printing paid
Opposition(s)19.02.2008No opposition filed within time limit [2008/17]
Fees paidRenewal fee
31.03.2005Renewal fee patent year 03
30.03.2006Renewal fee patent year 04
30.03.2007Renewal fee patent year 05
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Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court.
Cited inInternational search[X]WO0199163  (KONINKL PHILIPS ELECTRONICS NV [NL]) [X] 1-20 * figure 2 *;
 [X]US6037621  (WILSON WILLIAM BURDETT [US]) [X] 1-20 * the whole document *;
 [X]DE10046910  (MITSUBISHI ELECTRIC CORP [JP]) [X] 1-20 * the whole document *;
 [DX]US5583359  (NG ANTHONY C C [CA], et al) [DX] 1-20 * the whole document *;
 [A]WO0191144  (CONEXANT SYSTEMS INC [US]) [A] * the whole document *;
 [DA]DE19850915  (BOSCH GMBH ROBERT [DE]) [DA] * the whole document *;
 [DA]US5208725  (AKCASU OSMAN E [US]) [DA] * the whole document *;
 [A]US6297524  (VATHULYA VICKRAM [US], et al) [A] * the whole document *
 [DA]  - APARICIO R ET AL, "Capacity limits and matching properties of integrated capacitors", PROCEEDINGS OF THE IEEE 2001 CUSTOM INTEGRATED CIRCUITS CONFERENCE, SAN DIEGO, CA, USA, 6-9 MAY 2001, IEEE Journal of Solid-State Circuits, March 2002, IEEE, USA, vol. 37, no. 3, ISSN 0018-9200, pages 384 - 393, XP002252607 [DA] * the whole document *

DOI:   http://dx.doi.org/10.1109/4.987091
The EPO accepts no responsibility for the accuracy of data originating from other authorities; in particular, it does not guarantee that it is complete, up to date or fit for specific purposes.