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Extract from the Register of European Patents

EP About this file: EP1548619

EP1548619 - Method and device for automated layer generation for double-gate finFET designs [Right-click to bookmark this link]
StatusThe application is deemed to be withdrawn
Status updated on  17.02.2012
Database last updated on 28.09.2024
Most recent event   Tooltip17.02.2012Application deemed to be withdrawnpublished on 21.03.2012  [2012/12]
Applicant(s)For all designated states
International Business Machines Corporation
New Orchard Road
Armonk, NY 10504 / US
[N/P]
Former [2005/26]For all designated states
International Business Machines Corporation
New Orchard Road
Armonk, N.Y. 10504 / US
Inventor(s)01 / ALLER, Ingo
Hegelstrasse 12
71093, Weil im Schönbuch / DE
02 / GERNHOEFER, Veit
Nuertinger Str. 14
71032, Boeblingen / DE
03 / KEINERT, Joachim
Hoelderlinstr. 27
71155, Altdorf / DE
04 / LUDWIG, Thomas
Im Winkel 10
71063, Sindelfingen / DE
 [2005/26]
Representative(s)Teufel, Fritz
IBM Deutschland Management & Business Support GmbH
Patentwesen u. Urheberrecht
71137 Ehningen / DE
[N/P]
Former [2009/38]Teufel, Fritz
IBM Deutschland Management & Business Support GmbH Patentwesen u. Urheberrecht
71137 Ehningen / DE
Former [2008/37]Teufel, Fritz
IBM Deutschland GmbH Intellectual Property
70548 Stuttgart / DE
Former [2005/26]Teufel, Fritz, Dipl.-Phys.
IBM Deutschland GmbH, Intellectual Property, Pascalstrasse 100
70548 Stuttgart / DE
Application number, filing date04106287.803.12.2004
[2005/26]
Priority number, dateEP2003010492122.12.2003         Original published format: EP 03104921
[2006/49]
Former [2005/26]EP3104921622.12.2003
Filing languageEN
Procedural languageEN
PublicationType: A2 Application without search report 
No.:EP1548619
Date:29.06.2005
Language:EN
[2005/26]
Type: A3 Search report 
No.:EP1548619
Date:13.05.2009
[2009/20]
Search report(s)(Supplementary) European search report - dispatched on:EP17.04.2009
ClassificationIPC:G06F17/50
[2005/26]
CPC:
H01L21/84 (EP); G06F30/39 (EP); H01L29/7851 (EP)
Designated contracting statesAT,   BE,   BG,   CH,   CY,   CZ,   DE,   DK,   EE,   ES,   FI,   FR,   GB,   GR,   HU,   IE,   IS,   IT,   LI,   LT,   LU,   MC,   NL,   PL,   PT,   RO,   SE,   SI,   SK,   TR [2005/26]
TitleGerman:Verfahren und Vorrichtung zur automatisierten Erzeugung von Schichten von Doppel-Gate-FinFET-Entwürfen[2005/26]
English:Method and device for automated layer generation for double-gate finFET designs[2005/26]
French:Méthode et dispositif pour la génération automatique de couches pour des conceptions de FinFET à double grille[2005/26]
Examination procedure06.05.2009Examination requested  [2009/25]
20.05.2011Despatch of a communication from the examining division (Time limit: M04)
01.10.2011Application deemed to be withdrawn, date of legal effect  [2012/12]
07.11.2011Despatch of communication that the application is deemed to be withdrawn, reason: reply to the communication from the examining division not received in time  [2012/12]
Divisional application(s)The date of the Examining Division's first communication in respect of the earliest application for which a communication has been issued is  20.05.2011
Fees paidRenewal fee
19.12.2006Renewal fee patent year 03
17.12.2007Renewal fee patent year 04
12.12.2008Renewal fee patent year 05
16.12.2009Renewal fee patent year 06
16.12.2010Renewal fee patent year 07
Penalty fee
Additional fee for renewal fee
31.12.201108   M06   Not yet paid
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Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court.
Documents cited:Search[A]WO9530198  (CADENCE DESIGN SYSTEMS INC [US]) [A] 1,6,11,15 * page 9, line 15 - page 13, line 3 * * figure 2 *;
 [A]US2003145299  (FRIED DAVID M [US], et al) [A] 1,6,11,15 * paragraphs [0008] - [0013] ** figure 1 *
The EPO accepts no responsibility for the accuracy of data originating from other authorities; in particular, it does not guarantee that it is complete, up to date or fit for specific purposes.