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Extract from the Register of European Patents

EP About this file: EP1608012

EP1608012 - METHOD OF FORMING TRENCH ISOLATION STRUCTURE [Right-click to bookmark this link]
StatusThe application has been withdrawn
Status updated on  16.11.2007
Database last updated on 11.09.2024
Most recent event   Tooltip15.08.2008Change - representativepublished on 17.09.2008  [2008/38]
Applicant(s)For all designated states
AZ Electronic Materials USA Corp.
70 Meister Avenue
Somerville, NJ 08876 / US
[2005/51]
Inventor(s)01 / ICHIYAMA, Masaaki C/o AZ Electronic Materials
(Japan) K.K. 3330, Chihama, Daito-cho, Ogasa-gun
Shizuoka 437-1412 / JP
02 / NAGURA, Teruno C/o AZ Electronic Materials
(Japan) K.K. 3330, Chihama, Daito-cho, Ogasa-gun
Shizuoka 437-1412 / JP
03 / ISHIKAWA, Tomonori C/o AZ Electronic Materials
(Japan) K.K., Bunkyo Green Court, 28-8 Honkomagome
2-chome, Bunkyo-ku, Tokyo 113-0021 / JP
04 / SAKURAI, Takaaki C/o AZ Electronic Materials
(Japan) K.K., Bunkyo Green Court, 28-8 Honkomagome
2-chome, Bunkyo- ku, Tokyo 113-0021 / JP
05 / SHIMIZU, Yasuo C/o AZ Electronic Materials
(Japan) K.K.3330, Chihama, Daito-cho
Ogasa-gun, Shizuoka 437-1412 / JP
 [2005/51]
Representative(s)Isenbruck, Günter
Patentanwälte
Isenbruck Bösl Hörschler PartG mbB
Eastsite One
Seckenheimer Landstrasse 4
68163 Mannheim / DE
[N/P]
Former [2008/38]Isenbruck, Günter
Isenbruck, Bösl, Hörschler, Wichmann, Huhn Patentanwälte Theodor-Heuss-Anlage 12
68165 Mannheim / DE
Former [2005/51]Isenbruck, Günter
Patentanwälte, Isenbruck - Bösl - Hörschler - Wichmann - Huhn, Theodor-Heuss-Anlage 12
68165 Mannheim / DE
Application number, filing date04716765.503.03.2004
[2005/51]
WO2004JP02638
Priority number, dateJP2003005836505.03.2003         Original published format: JP 2003058365
[2005/51]
Filing languageJA
Procedural languageEN
PublicationType: A1 Application with search report
No.:WO2004079819
Date:16.09.2004
Language:EN
[2004/38]
Type: A1 Application with search report 
No.:EP1608012
Date:21.12.2005
Language:EN
The application published by WIPO in one of the EPO official languages on 16.09.2004 takes the place of the publication of the European patent application.
[2005/51]
Search report(s)International search report - published on:JP16.09.2004
ClassificationIPC:H01L21/762
[2005/51]
CPC:
H01L21/76224 (EP,US); H01L21/762 (KR)
Designated contracting statesAT,   BE,   BG,   CH,   CY,   CZ,   DE,   DK,   EE,   ES,   FI,   FR,   GB,   GR,   HU,   IE,   IT,   LI,   LU,   MC,   NL,   PL,   PT,   RO,   SE,   SI,   SK,   TR [2005/51]
Extension statesALNot yet paid
LTNot yet paid
LVNot yet paid
MKNot yet paid
TitleGerman:VERFAHREN ZUR BIILDUNG EINER GRABENISOLATIONSSTRUKTUR[2005/51]
English:METHOD OF FORMING TRENCH ISOLATION STRUCTURE[2005/51]
French:PROCEDE DE FORMATION D'UNE STRUCTURE D'ISOLATION DE TRANCHEE[2005/51]
Entry into regional phase04.10.2005Translation filed 
04.10.2005National basic fee paid 
04.10.2005Search fee paid 
04.10.2005Designation fee(s) paid 
04.10.2005Examination fee paid 
Examination procedure24.12.2004Request for preliminary examination filed
International Preliminary Examining Authority: JP
04.10.2005Examination requested  [2005/51]
13.11.2007Application withdrawn by applicant  [2007/51]
Fees paidRenewal fee
29.06.2006Renewal fee patent year 03
30.03.2007Renewal fee patent year 04
Penalty fee
Additional fee for renewal fee
31.03.200603   M06   Fee paid on   29.06.2006
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Patent Court
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Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court.
Cited inInternational search[Y]JPS6265437  (SONY CORP);
 [Y]JPH03101148  (MITSUBISHI ELECTRIC CORP);
 [Y]JPH0497542  (NEC CORP);
 [Y]JP2000114362  (NEC CORP);
 [Y]JP2001203264  (NEC CORP);
 [Y]JP2001308090  (TONENGENERAL SEKIYU KK);
 [Y]JP2002170877  (SHARP KK);
 [Y]JP2003507887  ;
 [A]  - HEO J-H, ET AL, "Void free and low stress shallow trench isolation technology using P-SOG for sub 0.1 mum device", 2002 SYMPOSIUM ON VLSI TECHNOLOGY DIGEST OF TECHNICAL PAPERS, (200206), pages 132 - 133, XP001109849
 [AP]  - HEO J-H, ET AL, "The P-SOG filling shallow trench isolation technology for sub-70nm device", 2003 SYMPOSIUM ON VLSI TECHNOLOGY DIGEST OF TECHNICAL PAPERS, (200306), pages 155 - 156, XP002980514
 [AP]  - CHOI J-S, ET AL, "A shallow trench isolation using novel polysilazane-based SOG for deep-submicron technologies and beyond", 2003 IEEE INTERNATIONAL SYMPOSIUM ON SEMICONDUCTOR MANUFACTURING, (200310), pages 419 - 422, XP010667486

DOI:   http://dx.doi.org/10.1109/ISSM.2003.1243316
The EPO accepts no responsibility for the accuracy of data originating from other authorities; in particular, it does not guarantee that it is complete, up to date or fit for specific purposes.