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EP1627470

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Extract from the Register of European Patents

EP About this file: EP1627470

EP1627470 - INTEGRATED CIRCUIT COMPRISING AN ENERGY SAVING MODE AND METHOD FOR OPERATING SAID CIRCUIT [Right-click to bookmark this link]
Status	No opposition filed within time limit Status updated on 09.01.2009 Database last updated on 30.09.2024
Most recent event Tooltip	09.01.2009	No opposition filed within time limit	published on 11.02.2009 [2009/07]
Applicant(s)	For all designated states Infineon Technologies AG St.-Martin-Strasse 53 81669 München / DE
	[2006/08]
Inventor(s)	01 / GAMMEL, Berndt, M. Dr. Brenner-Str. 16 85570 Markt Schwaben / DE
	02 / KÜNEMUND, Thomas Strassbergerstr. 73 80809 München / DE
	[2007/03]
Former [2006/08]	01 / GAMMEL, Berndt, M. Dr. Brenner-Str. 16 85570 Markt Schwaben / DE
	02 / KÜNEMUND, Thomas Lindwurmstr. 129c 80337 München / DE
Representative(s)	Epping - Hermann - Fischer Patentanwaltsgesellschaft mbH Schlossschmidstrasse 5 80639 München / DE
	[N/P]
Former [2006/08]	Epping - Hermann - Fischer Ridlerstrasse 55 80339 München / DE
Application number, filing date	04727231.5	14.04.2004
	[2006/08]
	WO2004DE00768
Priority number, date	DE2003123861	26.05.2003 Original published format: DE 10323861
	[2006/08]
Filing language	DE
Procedural language	DE
Publication	Type:	A1 Application with search report
	No.:	WO2004109921
	Date:	16.12.2004
	Language:	DE
	[2004/51]
	Type:	A1 Application with search report
	No.:	EP1627470
	Date:	22.02.2006
	Language:	DE
	The application published by WIPO in one of the EPO official languages on 16.12.2004 takes the place of the publication of the European patent application.
	[2006/08]
	Type:	B1 Patent specification
	No.:	EP1627470
	Date:	05.03.2008
	Language:	DE
	[2008/10]
Search report(s)	International search report - published on:	EP	16.12.2004
Classification	IPC:	H03K19/00	[2006/08]
	CPC:	H03K19/0016 (EP,US); H03K21/403 (EP,US)
Designated contracting states	DE, FR [2006/35]
Former [2006/08]	AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HU, IE, IT, LI, LU, MC, NL, PL, PT, RO, SE, SI, SK, TR
Extension states	AL	Not yet paid
	HR	Not yet paid
	LT	Not yet paid
	LV	Not yet paid
	MK	Not yet paid
Title	German:	INTEGRIERTE SCHALTUNG MIT STROMSPARMODUS UND VERFAHREN ZUM BETREIBEN DER INTEGRIERTEN SCHALTUNG	[2006/08]
	English:	INTEGRATED CIRCUIT COMPRISING AN ENERGY SAVING MODE AND METHOD FOR OPERATING SAID CIRCUIT	[2006/08]
	French:	CIRCUIT INTEGRE POUVANT FONCTIONNER EN MODE ECONOMIE DE COURANT, ET PROCEDE POUR FAIRE FONCTIONNER CE CIRCUIT INTEGRE	[2006/08]
Entry into regional phase	22.04.2005	National basic fee paid
	22.04.2005	Designation fee(s) paid
	22.04.2005	Examination fee paid
Examination procedure	13.12.2004	Request for preliminary examination filed International Preliminary Examining Authority: EP
	22.04.2005	Examination requested [2006/08]
	20.02.2006	Despatch of a communication from the examining division (Time limit: M06)
	21.08.2006	Reply to a communication from the examining division
	24.09.2007	Communication of intention to grant the patent
	14.01.2008	Fee for grant paid
	14.01.2008	Fee for publishing/printing paid
Opposition(s)	08.12.2008	No opposition filed within time limit [2009/07]
Fees paid	Renewal fee
	29.03.2006	Renewal fee patent year 03
	17.04.2007	Renewal fee patent year 04
Opt-out from the exclusive Tooltip competence of the Unified Patent Court	See the Register of the Unified Patent Court for opt-out data
	Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court.
Cited in	International search	[X]US2002186040 (OOISHI TSUKASA [JP]) [X] 1-4,12-14,16 * paragraphs [0062] - [0066] - [0078] , [0093] - [0095] - [0103] - [0106] - [0178]; figures 1,2,4,5,6A,6B,7,27 *;
		[X]EP0964519 (NEC CORP [JP]) [X] 1-3,12-14,16 * paragraphs [0067] - [0105]; figures 2,3A-3E *;
		[X]EP0993116 (NEC CORP [JP]) [X] 1-3,16 * paragraphs [0056] - [0110]; figures 3,4,5A-5G,6A-6G *;
		[A]US2002105845 (HIDAKA HIDETO [JP]) [A] 1,16 * figures 2-6,16,19-21 *;
		[A]US2002060947 (HATAE HIROSHI [JP]) [A] 1,16 * figures 1,4,5 *
		[X] - SHIGEMATSU S ET AL, "A 1-V HIGH-SPEED MTCMOS CIRCUIT SCHEME FOR POWER-DOWN APPLICATION CIRCUITS", IEEE JOURNAL OF SOLID-STATE CIRCUITS, IEEE INC. NEW YORK, US, (19970601), vol. 32, no. 6, ISSN 0018-9200, pages 861 - 869, XP000723409 [X] 1-3,16 * figure 2 * DOI: http://dx.doi.org/10.1109/4.585288

The EPO accepts no responsibility for the accuracy of data originating from other authorities; in particular, it does not guarantee that it is complete, up to date or fit for specific purposes.

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