EP1601130 - Delay locked loop circuitry for clock delay adjustment [Right-click to bookmark this link] | Status | No opposition filed within time limit Status updated on 16.10.2009 Database last updated on 03.09.2024 | Most recent event Tooltip | 16.10.2009 | No opposition filed within time limit | published on 18.11.2009 [2009/47] | Applicant(s) | For all designated states Rambus, Inc. 4440 El Camino Real Los Altos, CA 94022 / US | [2005/48] | Inventor(s) | 01 /
Donnelly, Kevin S. 762 Edgewood Lane Los Altos, CA 94022 / US | 02 /
Chau, Pak Shing 1677 Klipspringer Drive San Jose, CA 95124 / US | 03 /
Horowitz, Mark A. 1309 San Mateo Drive Menlo Park, CA 94025 / US | 04 /
Lee, Thomas H. 939 Bubb Road Cupertino, CA 95014 / US | 05 /
Johnson, Mark G. 125 Arbuelo Way Los Altos, CA 94022 / US | 06 /
Lau, Benedict C. 5277 | 07 /
Yu, Leung 2952 Gala Court Santa Clara, CA 95051 / US | 08 /
Garlepp, Bruno W. 5193 Rhonda Drive San Jose, CA 95129 / US | 09 /
Chan, Yiu-Fai 27275 Julietta Lane Los Altos Hills, CA 94022 / US | 10 /
Kim, Jun 6 Knot Lane Redwood City, CA 94065 / US | 11 /
Tran, Chanh Vi 3009 Breen Court San Jose, CA 95121 / US | 12 /
Stark, Donald C. 201 High Street Palo Alto, CA 94301 / US | [2007/26] |
Former [2006/16] | 01 /
Donnelly, Kevin S. 1671 Noe Street San Francisco, CA 94131 / US | ||
02 /
Chau, Pak Shing 1677 Klipspringer Drive San Jose, CA 95124 / US | |||
03 /
Horowitz, Mark A. 1309 San Mateo Drive Menlo Park, CA 94025 / US | |||
04 /
Lee, Thomas H. 939 Bubb Road Cupertino, CA 95014 / US | |||
05 /
Johnson, Mark G. 125 Arbuelo Way Los Altos, CA 94022 / US | |||
06 /
Lau, Benedict C. 5277 | |||
07 /
Yu, Leung 2952 Gala Court Santa Clara, CA 95051 / US | |||
08 /
Garlepp, Bruno W. 5193 Rhonda Drive San Jose, CA 95129 / US | |||
09 /
Chan, Yiu-Fai 27275 Julietta Lane Los Altos Hills, CA 94022 / US | |||
10 /
Kim, Jun 6 Knot Lane Redwood City, CA 94065 / US | |||
11 /
Tran, Chanh Vi 3009 Breen Court San Jose, CA 95121 / US | |||
12 /
Stark, Donald C. 201 High Street Palo Alto, CA 94301 / US | |||
Former [2005/48] | 01 /
Donnelly, Kevin S. 1671 Noe Street San Francisco, CA 94131 / US | ||
02 /
Chau, Pak Shing 1677 Klipspringer Drive San Jose, CA 95124 / US | |||
03 /
Horowitz, Mark A. 1309 San Mateo Drive Menlo Park, CA 94025 / US | |||
04 /
Lee, Thomas H. 939 Bubb Road Cupertino, CA 95014 / US | |||
05 /
Johnson, Mark G. 125 Arbuelo Way Los Altos, CA 94022 / US | |||
06 /
Lau, Benedict C. 630 Celebration Court San Jose, CA 95134 / US | |||
07 /
Yu, Leung 2952 Gala Court Santa Clara, CA 95051 / US | |||
08 /
Garlepp, Bruno W. 99 E. Middlefield Road 48 Mountain View, CA 94043 / US | |||
09 /
Chan, Yiu-Fai 27275 Julietta Lane Los Altos Hills, CA 94022 / US | |||
10 /
Kim, Jun 6 Knot Lane Redwood City, CA 94065 / US | |||
11 /
Tran, Chanh Vi 3009 Breen Court San Jose, CA 95121 / US | |||
12 /
Stark, Donald C. 201 High Street Palo Alto, CA 94301 / US | Representative(s) | Eisenführ Speiser Patentanwälte Rechtsanwälte PartGmbB Johannes-Brahms-Platz 1 20355 Hamburg / DE | [N/P] |
Former [2009/28] | Eisenführ, Speiser & Partner Johannes-Brahms-Platz 1 20355 Hamburg / DE | ||
Former [2008/40] | Eisenführ, Speiser & Partner Patentanwälte Rechtsanwälte Postfach 10 60 78 28060 Bremen / DE | ||
Former [2005/48] | Eisenführ, Speiser & Partner Patentanwälte Rechtsanwälte Postfach 10 60 78 28060 Bremen / DE | Application number, filing date | 05018741.8 | 04.02.1998 | [2005/48] | Priority number, date | US19970795657 | 06.02.1997 Original published format: US 795657 | [2005/48] | Filing language | EN | Procedural language | EN | Publication | Type: | A2 Application without search report | No.: | EP1601130 | Date: | 30.11.2005 | Language: | EN | [2005/48] | Type: | A3 Search report | No.: | EP1601130 | Date: | 28.02.2007 | [2007/09] | Type: | B1 Patent specification | No.: | EP1601130 | Date: | 10.12.2008 | Language: | EN | [2008/50] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 31.01.2007 | Classification | IPC: | H04L7/00, H03L7/081, H03L7/07, G11C7/22 | [2005/48] | CPC: |
H03K5/133 (EP,US);
G06F1/10 (EP,US);
G11C7/22 (EP,US);
G11C7/222 (EP,US);
H03K5/2481 (EP,US);
H03L7/07 (EP,US);
H03L7/0805 (EP,US);
H03L7/0814 (EP,US);
H03L7/0816 (EP,US);
H04L7/0037 (EP,US);
H03K2005/00026 (EP,US);
H03K2005/00032 (EP,US);
H03K2005/00052 (EP,US);
H03K2005/00208 (EP,US);
H04L7/0008 (EP,US);
H04L7/0025 (EP,US)
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| Designated contracting states | DE, GB, IT [2007/44] |
Former [2005/48] | AT, BE, CH, DE, DK, ES, FI, FR, GB, GR, IE, IT, LI, LU, MC, NL, PT, SE | Title | German: | Schaltung mit Verzögerungsregelschleife zur Anpassung der Taktverzögerung | [2005/48] | English: | Delay locked loop circuitry for clock delay adjustment | [2005/48] | French: | Circuit à boucles à retard de phase servant à régler un retard d'horloge | [2005/48] | Examination procedure | 28.08.2007 | Examination requested [2007/41] | 16.10.2007 | Despatch of a communication from the examining division (Time limit: M06) | 25.04.2008 | Reply to a communication from the examining division | 17.06.2008 | Communication of intention to grant the patent | 21.10.2008 | Fee for grant paid | 21.10.2008 | Fee for publishing/printing paid | Parent application(s) Tooltip | EP98906112.2 / EP1031203 | Opposition(s) | 11.09.2009 | No opposition filed within time limit [2009/47] | Fees paid | Renewal fee | 30.12.2005 | Renewal fee patent year 03 | 30.12.2005 | Renewal fee patent year 04 | 30.12.2005 | Renewal fee patent year 05 | 30.12.2005 | Renewal fee patent year 06 | 30.12.2005 | Renewal fee patent year 07 | 30.12.2005 | Renewal fee patent year 08 | 27.02.2006 | Renewal fee patent year 09 | 27.02.2007 | Renewal fee patent year 10 | 25.02.2008 | Renewal fee patent year 11 | 14.03.2008 | Renewal fee patent year 12 |
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Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [DA]US5485490 (LEUNG WINGYU [US], et al) [DA] 1-54 * column 2, line 33 - line 38 * * column 3, line 34 - line 45 * * column 8, line 1 - line 14 * * column 4, line 3 - line 46 * * column 4, line 52 - column 5, line 7 * * column 6, line 37 - line 44 ** figures 1,2,4,6 *; | [DXA] - TANOI S ET AL, "A 250-622 MHZ DESKEW AND JITTER-SUPPRESSED CLOCK BUFFER USING TWO-LOOP ARCHITECTURE", IEEE JOURNAL OF SOLID-STATE CIRCUITS, IEEE SERVICE CENTER, PISCATAWAY, NJ, US, (19960401), vol. 31, no. 4, ISSN 0018-9200, pages 487 - 493, XP000597219 [DX] 1,17,29,40,54 * page 487, column R, paragraph 2 - paragraph 4 * * page 488, column R, paragraph 2 * * page 489, column L, paragraph 2 - column R, paragraph 2; figures 1,3,5,6 * [A] 2-16,18-28,30-39,42-53 DOI: http://dx.doi.org/10.1109/4.499724 |