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EP1612943
European procedure
Extract from the Register of European Patents
EP About this file: EP1612943
| EP1612943 - PLL circuit and phase control method of PLL circuit [Right-click to bookmark this link] | Status | No opposition filed within time limit Status updated on 17.10.2008 Database last updated on 09.09.2024 | Most recent event Tooltip | 17.10.2008 | No opposition filed within time limit | published on 19.11.2008 [2008/47] | Applicant(s) | For all designated states NEC Corporation 7-1, Shiba 5-chome Minato-ku Tokyo 108-8001 / JP | [N/P] |
| Former [2006/01] | For all designated states NEC CORPORATION 7-1, Shiba 5-chome, Minato-ku Tokyo 108 / JP | Inventor(s) | 01 /
Takahashi, Masayuki, c/o Nec Com. Systems, Ltd. 4-28 Mita 1-chome Minato-ku Tokyo / JP | [2006/01] | Representative(s) | Moir, Michael Christopher, et al Mathys & Squire LLP 120 Holborn London EC1N 2SQ / GB | [N/P] |
| Former [2006/01] | Moir, Michael Christopher, et al Mathys & Squire, 120 Holborn London EC1N 2SQ / GB | Application number, filing date | 05254016.8 | 28.06.2005 | [2006/01] | Priority number, date | JP20040189581 | 28.06.2004 Original published format: JP 2004189581 | [2006/01] | Filing language | EN | Procedural language | EN | Publication | Type: | A1 Application with search report | No.: | EP1612943 | Date: | 04.01.2006 | Language: | EN | [2006/01] | Type: | B1 Patent specification | No.: | EP1612943 | Date: | 12.12.2007 | Language: | EN | [2007/50] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 12.09.2005 | Classification | IPC: | H03L7/085, H03L7/093, G01R25/00, G01R25/04 | [2006/01] | CPC: |
H03L7/085 (EP,US);
H03L7/093 (EP,US)
| Designated contracting states | FR, GB [2006/36] |
| Former [2006/01] | AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HU, IE, IS, IT, LI, LT, LU, MC, NL, PL, PT, RO, SE, SI, SK, TR | Title | German: | Phasenregelkreis und Verfahren zur Phasenregelung dafür | [2006/01] | English: | PLL circuit and phase control method of PLL circuit | [2006/01] | French: | Boucle à verrouillage de phase, et procédé de réglage de phase correspondante | [2006/01] | Examination procedure | 11.11.2005 | Examination requested [2006/02] | 23.02.2006 | Despatch of a communication from the examining division (Time limit: M04) | 26.06.2006 | Reply to a communication from the examining division | 01.09.2006 | Despatch of a communication from the examining division (Time limit: M03) | 03.11.2006 | Reply to a communication from the examining division | 06.07.2007 | Communication of intention to grant the patent | 22.10.2007 | Fee for grant paid | 22.10.2007 | Fee for publishing/printing paid | Opposition(s) | 15.09.2008 | No opposition filed within time limit [2008/47] | Fees paid | Renewal fee | 30.05.2007 | Renewal fee patent year 03 |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [XA]US4975634 (SHOHET YUVAL [US]) [X] 1,4,7,9 * column 1, line 47 - column 4, line 28; figures 1,2 * [A] 2,3,5,6,8,10; | [A]US5991350 (YAMAMOTO KOJI [JP]) [A] 1-10 * column 2, line 52 - column 3, line 67; figure 1 *; | [A]US6441601 (CLARK JAMES M [US], et al) [A] 1-10* column 9, line 63 - column 11, line 39; figures 4,7 * |