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Extract from the Register of European Patents

EP About this file: EP1706752

EP1706752 - JTAG TEST ARCHITECTURE FOR MULTI-CHIP PACK [Right-click to bookmark this link]
StatusNo opposition filed within time limit
Status updated on  13.03.2009
Database last updated on 07.10.2024
Most recent event   Tooltip30.09.2011Lapse of the patent in a contracting state
New state(s): CY, TR		published on 02.11.2011  [2011/44]
Applicant(s)For all designated states
NXP B.V.
High Tech Campus 60
5656 AG Eindhoven / NL
[2007/31]
Former [2006/40]For all designated states
Koninklijke Philips Electronics N.V.
Groenewoudseweg 1
5621 BA Eindhoven / NL
Inventor(s)01 / TALAYSSAT, Jacky, c/o Société Civile SPID
156 Boulevard Haussmann
F-75008 PARIS / FR
02 / BUWALDA, Sake, c/o Société Civile SPID
156 Boulevard Haussmann
F-75008 PARIS / FR
 [2006/40]
Representative(s)Williamson, Paul Lewis, et al
NXP Semiconductors
Intellectual Property and Licensing
Red Central
60 High Street, Redhill
Surrey RH1 1NY / GB
[N/P]
Former [2009/09]Williamson, Paul Lewis, et al
NXP Semiconductors UK Ltd. Intellectual Property Department Betchworth House Station Road Redhill
Surrey RH1 1DL / GB
Former [2007/01]White, Andrew Gordon, et al
NXP Semiconductors Intellectual Property Department Cross Oak Lane
Redhill, Surrey RH1 5HA / GB
Former [2006/49]van Oudheusden-Perset, Laure E., et al
Société Civile SPID 156, Boulevard Haussmann
75008 Paris / FR
Former [2006/40]Chaffraix, Jean
Société Civile SPID, 156, Boulevard Haussmann
75008 Paris / FR
Application number, filing date05702239.405.01.2005
[2006/40]
WO2005IB00072
Priority number, dateEP2004030001613.01.2004         Original published format: EP 04300016
[2006/40]
Filing languageEN
Procedural languageEN
PublicationType: A1 Application with search report
No.:WO2005069025
Date:28.07.2005
Language:EN
[2005/30]
Type: A1 Application with search report 
No.:EP1706752
Date:04.10.2006
Language:EN
The application published by WIPO in one of the EPO official languages on 28.07.2005 takes the place of the publication of the European patent application.
[2006/40]
Type: B1 Patent specification 
No.:EP1706752
Date:07.05.2008
Language:EN
[2008/19]
Search report(s)International search report - published on:EP28.07.2005
ClassificationIPC:G01R31/3185
[2006/40]
CPC:
G01R31/318558 (EP,US); G01R31/3183 (KR); G01R31/26 (KR);
G01R31/318536 (EP,US); H01L22/00 (KR)
Designated contracting statesAT,   BE,   BG,   CH,   CY,   CZ,   DE,   DK,   EE,   ES,   FI,   FR,   GB,   GR,   HU,   IE,   IS,   IT,   LI,   LT,   LU,   MC,   NL,   PL,   PT,   RO,   SE,   SI,   SK,   TR [2006/40]
Extension statesALNot yet paid
BANot yet paid
HRNot yet paid
LVNot yet paid
MKNot yet paid
YUNot yet paid
TitleGerman:JTAG-TESTARCHITEKTUR FÜR EIN MEHRCHIP-PACK[2006/40]
English:JTAG TEST ARCHITECTURE FOR MULTI-CHIP PACK[2006/40]
French:ARCHITECTURE DE TEST JTAG POUR BOITIER MULTIPUCE[2006/40]
Entry into regional phase14.08.2006National basic fee paid 
14.08.2006Designation fee(s) paid 
14.08.2006Examination fee paid 
Examination procedure14.08.2006Examination requested  [2006/40]
10.11.2006Despatch of a communication from the examining division (Time limit: M04)
19.01.2007Reply to a communication from the examining division
03.04.2007Despatch of a communication from the examining division (Time limit: M04)
02.08.2007Reply to a communication from the examining division
30.11.2007Communication of intention to grant the patent
18.03.2008Fee for grant paid
18.03.2008Fee for publishing/printing paid
Opposition(s)10.02.2009No opposition filed within time limit [2009/16]
Fees paidRenewal fee
31.01.2007Renewal fee patent year 03
31.01.2008Renewal fee patent year 04
Opt-out from the exclusive  Tooltip
competence of the Unified
Patent Court		 See the Register of the Unified Patent Court for opt-out data
Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court.
Lapses during opposition  TooltipAT07.05.2008
BE07.05.2008
CY07.05.2008
CZ07.05.2008
DK07.05.2008
EE07.05.2008
FI07.05.2008
IT07.05.2008
LT07.05.2008
NL07.05.2008
PL07.05.2008
RO07.05.2008
SI07.05.2008
SK07.05.2008
TR07.05.2008
BG07.08.2008
SE07.08.2008
GR08.08.2008
ES18.08.2008
IS07.09.2008
PT07.10.2008
HU08.11.2008
IE05.01.2009
LU05.01.2009
CH31.01.2009
LI31.01.2009
MC31.01.2009
[2011/43]
Former [2011/32]AT07.05.2008
BE07.05.2008
CZ07.05.2008
DK07.05.2008
EE07.05.2008
FI07.05.2008
IT07.05.2008
LT07.05.2008
NL07.05.2008
PL07.05.2008
RO07.05.2008
SI07.05.2008
SK07.05.2008
BG07.08.2008
SE07.08.2008
GR08.08.2008
ES18.08.2008
IS07.09.2008
PT07.10.2008
HU08.11.2008
IE05.01.2009
LU05.01.2009
CH31.01.2009
LI31.01.2009
MC31.01.2009
Former [2011/22]AT07.05.2008
BE07.05.2008
CZ07.05.2008
DK07.05.2008
EE07.05.2008
FI07.05.2008
IT07.05.2008
LT07.05.2008
NL07.05.2008
PL07.05.2008
RO07.05.2008
SI07.05.2008
SK07.05.2008
BG07.08.2008
SE07.08.2008
GR08.08.2008
ES18.08.2008
IS07.09.2008
PT07.10.2008
IE05.01.2009
LU05.01.2009
CH31.01.2009
LI31.01.2009
MC31.01.2009
Former [2010/52]AT07.05.2008
BE07.05.2008
CZ07.05.2008
DK07.05.2008
EE07.05.2008
FI07.05.2008
IT07.05.2008
LT07.05.2008
NL07.05.2008
PL07.05.2008
RO07.05.2008
SI07.05.2008
SK07.05.2008
BG07.08.2008
SE07.08.2008
GR08.08.2008
ES18.08.2008
IS07.09.2008
PT07.10.2008
IE05.01.2009
CH31.01.2009
LI31.01.2009
MC31.01.2009
Former [2010/07]AT07.05.2008
BE07.05.2008
CZ07.05.2008
DK07.05.2008
EE07.05.2008
FI07.05.2008
IT07.05.2008
LT07.05.2008
NL07.05.2008
PL07.05.2008
RO07.05.2008
SI07.05.2008
SK07.05.2008
BG07.08.2008
SE07.08.2008
ES18.08.2008
IS07.09.2008
PT07.10.2008
IE05.01.2009
CH31.01.2009
LI31.01.2009
MC31.01.2009
Former [2009/48]AT07.05.2008
BE07.05.2008
CZ07.05.2008
DK07.05.2008
EE07.05.2008
FI07.05.2008
IT07.05.2008
LT07.05.2008
NL07.05.2008
PL07.05.2008
RO07.05.2008
SI07.05.2008
SK07.05.2008
BG07.08.2008
SE07.08.2008
ES18.08.2008
IS07.09.2008
PT07.10.2008
CH31.01.2009
LI31.01.2009
MC31.01.2009
Former [2009/27]AT07.05.2008
BE07.05.2008
CZ07.05.2008
DK07.05.2008
EE07.05.2008
FI07.05.2008
LT07.05.2008
NL07.05.2008
PL07.05.2008
RO07.05.2008
SI07.05.2008
SK07.05.2008
BG07.08.2008
SE07.08.2008
ES18.08.2008
IS07.09.2008
PT07.10.2008
Former [2009/22]AT07.05.2008
BE07.05.2008
CZ07.05.2008
DK07.05.2008
EE07.05.2008
FI07.05.2008
LT07.05.2008
NL07.05.2008
PL07.05.2008
RO07.05.2008
SI07.05.2008
SK07.05.2008
SE07.08.2008
ES18.08.2008
IS07.09.2008
PT07.10.2008
Former [2009/14]AT07.05.2008
BE07.05.2008
CZ07.05.2008
DK07.05.2008
FI07.05.2008
LT07.05.2008
NL07.05.2008
PL07.05.2008
RO07.05.2008
SI07.05.2008
SK07.05.2008
SE07.08.2008
ES18.08.2008
IS07.09.2008
PT07.10.2008
Former [2009/13]AT07.05.2008
BE07.05.2008
CZ07.05.2008
DK07.05.2008
FI07.05.2008
LT07.05.2008
NL07.05.2008
PL07.05.2008
SI07.05.2008
SK07.05.2008
SE07.08.2008
ES18.08.2008
IS07.09.2008
Former [2009/09]AT07.05.2008
DK07.05.2008
FI07.05.2008
NL07.05.2008
PL07.05.2008
SI07.05.2008
SE07.08.2008
ES18.08.2008
IS07.09.2008
Former [2009/07]AT07.05.2008
FI07.05.2008
NL07.05.2008
PL07.05.2008
SI07.05.2008
SE07.08.2008
ES18.08.2008
IS07.09.2008
Former [2009/05]AT07.05.2008
FI07.05.2008
NL07.05.2008
PL07.05.2008
SI07.05.2008
ES18.08.2008
IS07.09.2008
Former [2008/49]AT07.05.2008
FI07.05.2008
NL07.05.2008
PL07.05.2008
SI07.05.2008
ES18.08.2008
Former [2008/48]NL07.05.2008
SI07.05.2008
ES18.08.2008
Former [2008/44]SI07.05.2008
Cited inInternational search[A]US5491666  (STURGES JAY [US]) [A] 1-20* column 9, line 32 - column 10, line 31; figure 6; claim 1 *;
 [X]US5862152  (HANDLY PAUL ROBERT [US], et al) [X] 1-20 * column 1, line 19 - column 5, line 8; figure 2 *;
 [A]  - HILLA S C ED - INSTITUTE OF ELECTRICAL AND ELECTRONICS ENGINEERS, "BOUNDARY SCAN TESTING FOR MULTICHIP MODULES", PROCEEDINGS OF THE INTERNATIONAL TEST CONFERENCE. BALTIMORE, SEPT. 20, (19920920), vol. CONF. 23, ISBN 0-7803-0760-7, pages 224 - 231, XP000348757 [A] 1-20 * the whole document *
The EPO accepts no responsibility for the accuracy of data originating from other authorities; in particular, it does not guarantee that it is complete, up to date or fit for specific purposes.