blank Quick help
blank Maintenance news

Scheduled maintenance

Regular maintenance outages:
between 05.00 and 05.15 hrs CET (Monday to Sunday).

Other outages
Availability
Register Forum

2022.02.11

More...
blank News flashes

News flashes

New version of the European Patent Register - SPC information for Unitary Patents.

2024-03-06

More...
blank Related links

Release notes
European Patent Register Assistant
European Patent Register Resource Book
European Patent Register – pocket guide
FAQ - European Patent Register
FAQ - Register Alert
Federated Register (Flyer)
Global Dossier (Flyer)
Register events
Deep link coverage
Federated Register content
The Patent Information Tour
Fair use charter

Extract from the Register of European Patents

EP About this file: EP1759380

EP1759380 - LOW POWER PROGRAMMABLE PROCESSOR [Right-click to bookmark this link]
StatusNo opposition filed within time limit
Status updated on  21.09.2012
Database last updated on 16.07.2024
Most recent event   Tooltip18.07.2014Lapse of the patent in a contracting state
New state(s): HU		published on 20.08.2014  [2014/34]
Applicant(s)For all designated states
NVIDIA Corporation
2701 San Tomas Expressway
Santa Clara, CA 95050 / US
[2007/10]
Inventor(s)01 / HUTCHINS, Edward, A.
1190 Morton Court
Mountain View, CA 94040 / US
02 / ANGELL, Brian, K.
1198 Cordelia Avenue
San Jose, CA 95129 / US
03 / KIM, Paul
38739 Logan Drive
Fremont, CA 94536 / US
 [2007/10]
Representative(s)Dilg, Andreas
Dilg, Haeusler, Schindelmann Patentanwaltsgesellschaft mbH Leonrodstrasse 58
80636 München / DE
[2011/46]
Former [2008/01]Dilg, Andreas
Dilg, Haeusler, Schindelmann Patentanwaltsgesellschaft mbH Nussbaumstrasse 6
80336 München / DE
Former [2007/10]Dilg, Andreas
Maiwald Patentanwalts GmbH Elisenhof Elisenstrasse 3
D-80335 München / DE
Application number, filing date05749863.613.05.2005
[2007/10]
WO2005US16967
Priority number, dateUS2004084609714.05.2004         Original published format: US 846097
US2004084611014.05.2004         Original published format: US 846110
US2004084622614.05.2004         Original published format: US 846226
US2004084633414.05.2004         Original published format: US 846334
US2004084610614.05.2004         Original published format: US 846106
US2004084571414.05.2004         Original published format: US 845714
[2007/10]
Filing languageEN
Procedural languageEN
PublicationType: A2 Application without search report
No.:WO2005114646
Date:01.12.2005
Language:EN
[2005/48]
Type: A2 Application without search report 
No.:EP1759380
Date:07.03.2007
Language:EN
The application published by WIPO in one of the EPO official languages on 01.12.2005 takes the place of the publication of the European patent application.
[2007/10]
Type: B1 Patent specification 
No.:EP1759380
Date:16.11.2011
Language:EN
[2011/46]
Search report(s)International search report - published on:US24.05.2007
(Supplementary) European search report - dispatched on:EP22.12.2008
ClassificationIPC:G09G5/37, G06T15/00
[2009/04]
CPC:
G06T15/005 (EP); G09G5/37 (KR); G06F15/76 (KR);
G06T1/20 (EP,KR)
Former IPC [2007/31]G09G5/37
Former IPC [2007/10]G09G5/37, G06F15/76
Designated contracting statesAT,   BE,   BG,   CH,   CY,   CZ,   DE,   DK,   EE,   ES,   FI,   FR,   GB,   GR,   HU,   IE,   IS,   IT,   LI,   LT,   LU,   MC,   NL,   PL,   PT,   RO,   SE,   SI,   SK,   TR [2007/10]
Extension statesAL04.12.2006
BA04.12.2006
HR04.12.2006
LV04.12.2006
MK04.12.2006
YU04.12.2006
TitleGerman:PROGRAMMIERBARER PROZESSOR MIT GERINGEM STROMVERBRAUCH[2007/10]
English:LOW POWER PROGRAMMABLE PROCESSOR[2007/10]
French:PROCESSEUR PROGRAMMABLE A FAIBLE CONSOMMATION D'ENERGIE[2007/10]
Entry into regional phase04.12.2006National basic fee paid 
04.12.2006Search fee paid 
04.12.2006Designation fee(s) paid 
04.12.2006Examination fee paid 
Examination procedure04.12.2006Examination requested  [2007/10]
27.07.2007Amendment by applicant (claims and/or description)
08.04.2009Despatch of a communication from the examining division (Time limit: M06)
02.09.2009Reply to a communication from the examining division
10.03.2010Despatch of a communication from the examining division (Time limit: M06)
08.09.2010Reply to a communication from the examining division
22.08.2011Communication of intention to grant the patent
30.09.2011Fee for grant paid
30.09.2011Fee for publishing/printing paid
Divisional application(s)The date of the Examining Division's first communication in respect of the earliest application for which a communication has been issued is  08.04.2009
Opposition(s)17.08.2012No opposition filed within time limit [2012/43]
Fees paidRenewal fee
14.05.2007Renewal fee patent year 03
28.03.2008Renewal fee patent year 04
12.05.2009Renewal fee patent year 05
31.03.2010Renewal fee patent year 06
11.05.2011Renewal fee patent year 07
Opt-out from the exclusive  Tooltip
competence of the Unified
Patent Court		 See the Register of the Unified Patent Court for opt-out data
Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court.
Lapses during opposition  TooltipHU13.05.2005
AT16.11.2011
BE16.11.2011
CY16.11.2011
CZ16.11.2011
DK16.11.2011
EE16.11.2011
FI16.11.2011
IT16.11.2011
LT16.11.2011
NL16.11.2011
PL16.11.2011
RO16.11.2011
SE16.11.2011
SI16.11.2011
SK16.11.2011
TR16.11.2011
BG16.02.2012
GR17.02.2012
ES27.02.2012
IS16.03.2012
PT16.03.2012
IE13.05.2012
LU13.05.2012
CH31.05.2012
FR31.05.2012
LI31.05.2012
MC31.05.2012
[2014/34]
Former [2014/27]AT16.11.2011
BE16.11.2011
CY16.11.2011
CZ16.11.2011
DK16.11.2011
EE16.11.2011
FI16.11.2011
IT16.11.2011
LT16.11.2011
NL16.11.2011
PL16.11.2011
RO16.11.2011
SE16.11.2011
SI16.11.2011
SK16.11.2011
TR16.11.2011
BG16.02.2012
GR17.02.2012
ES27.02.2012
IS16.03.2012
PT16.03.2012
IE13.05.2012
LU13.05.2012
CH31.05.2012
FR31.05.2012
LI31.05.2012
MC31.05.2012
Former [2014/21]AT16.11.2011
BE16.11.2011
CY16.11.2011
CZ16.11.2011
DK16.11.2011
EE16.11.2011
FI16.11.2011
IT16.11.2011
LT16.11.2011
NL16.11.2011
PL16.11.2011
RO16.11.2011
SE16.11.2011
SI16.11.2011
SK16.11.2011
TR16.11.2011
BG16.02.2012
GR17.02.2012
ES27.02.2012
IS16.03.2012
PT16.03.2012
IE13.05.2012
CH31.05.2012
FR31.05.2012
LI31.05.2012
MC31.05.2012
Former [2013/29]AT16.11.2011
BE16.11.2011
CY16.11.2011
CZ16.11.2011
DK16.11.2011
EE16.11.2011
FI16.11.2011
IT16.11.2011
LT16.11.2011
NL16.11.2011
PL16.11.2011
RO16.11.2011
SE16.11.2011
SI16.11.2011
SK16.11.2011
BG16.02.2012
GR17.02.2012
ES27.02.2012
IS16.03.2012
PT16.03.2012
IE13.05.2012
CH31.05.2012
FR31.05.2012
LI31.05.2012
MC31.05.2012
Former [2013/23]AT16.11.2011
BE16.11.2011
CY16.11.2011
CZ16.11.2011
DK16.11.2011
EE16.11.2011
IT16.11.2011
LT16.11.2011
NL16.11.2011
PL16.11.2011
RO16.11.2011
SE16.11.2011
SI16.11.2011
SK16.11.2011
BG16.02.2012
GR17.02.2012
ES27.02.2012
IS16.03.2012
PT16.03.2012
IE13.05.2012
CH31.05.2012
FR31.05.2012
LI31.05.2012
MC31.05.2012
Former [2013/22]AT16.11.2011
BE16.11.2011
CY16.11.2011
CZ16.11.2011
DK16.11.2011
EE16.11.2011
IT16.11.2011
LT16.11.2011
NL16.11.2011
PL16.11.2011
RO16.11.2011
SE16.11.2011
SI16.11.2011
SK16.11.2011
BG16.02.2012
GR17.02.2012
ES27.02.2012
IS16.03.2012
PT16.03.2012
IE13.05.2012
CH31.05.2012
LI31.05.2012
MC31.05.2012
Former [2013/20]AT16.11.2011
BE16.11.2011
CY16.11.2011
CZ16.11.2011
DK16.11.2011
EE16.11.2011
IT16.11.2011
LT16.11.2011
NL16.11.2011
PL16.11.2011
RO16.11.2011
SE16.11.2011
SI16.11.2011
SK16.11.2011
BG16.02.2012
GR17.02.2012
IS16.03.2012
PT16.03.2012
IE13.05.2012
CH31.05.2012
LI31.05.2012
MC31.05.2012
Former [2013/07]AT16.11.2011
BE16.11.2011
CY16.11.2011
CZ16.11.2011
DK16.11.2011
EE16.11.2011
IT16.11.2011
LT16.11.2011
NL16.11.2011
PL16.11.2011
RO16.11.2011
SE16.11.2011
SI16.11.2011
SK16.11.2011
BG16.02.2012
GR17.02.2012
IS16.03.2012
PT16.03.2012
CH31.05.2012
LI31.05.2012
MC31.05.2012
Former [2013/03]BE16.11.2011
CY16.11.2011
CZ16.11.2011
DK16.11.2011
EE16.11.2011
IT16.11.2011
LT16.11.2011
NL16.11.2011
PL16.11.2011
RO16.11.2011
SE16.11.2011
SI16.11.2011
SK16.11.2011
BG16.02.2012
GR17.02.2012
IS16.03.2012
PT16.03.2012
MC31.05.2012
Former [2012/37]BE16.11.2011
CY16.11.2011
CZ16.11.2011
DK16.11.2011
EE16.11.2011
IT16.11.2011
LT16.11.2011
NL16.11.2011
PL16.11.2011
RO16.11.2011
SE16.11.2011
SI16.11.2011
SK16.11.2011
BG16.02.2012
GR17.02.2012
IS16.03.2012
PT16.03.2012
Former [2012/36]BE16.11.2011
CY16.11.2011
CZ16.11.2011
DK16.11.2011
EE16.11.2011
LT16.11.2011
NL16.11.2011
PL16.11.2011
RO16.11.2011
SE16.11.2011
SI16.11.2011
SK16.11.2011
BG16.02.2012
GR17.02.2012
IS16.03.2012
PT16.03.2012
Former [2012/35]BE16.11.2011
CY16.11.2011
CZ16.11.2011
DK16.11.2011
EE16.11.2011
LT16.11.2011
NL16.11.2011
PL16.11.2011
SE16.11.2011
SI16.11.2011
BG16.02.2012
GR17.02.2012
IS16.03.2012
PT16.03.2012
Former [2012/34]BE16.11.2011
CY16.11.2011
CZ16.11.2011
LT16.11.2011
NL16.11.2011
PL16.11.2011
SE16.11.2011
SI16.11.2011
GR17.02.2012
IS16.03.2012
PT16.03.2012
Former [2012/28]BE16.11.2011
CY16.11.2011
LT16.11.2011
NL16.11.2011
PL16.11.2011
SE16.11.2011
SI16.11.2011
GR17.02.2012
IS16.03.2012
PT16.03.2012
Former [2012/26]BE16.11.2011
LT16.11.2011
NL16.11.2011
PL16.11.2011
SE16.11.2011
SI16.11.2011
GR17.02.2012
IS16.03.2012
PT16.03.2012
Former [2012/25]BE16.11.2011
LT16.11.2011
NL16.11.2011
SE16.11.2011
SI16.11.2011
GR17.02.2012
IS16.03.2012
PT16.03.2012
Former [2012/24]LT16.11.2011
NL16.11.2011
SE16.11.2011
SI16.11.2011
GR17.02.2012
IS16.03.2012
PT16.03.2012
Former [2012/23]LT16.11.2011
NL16.11.2011
GR17.02.2012
IS16.03.2012
PT16.03.2012
Former [2012/21]LT16.11.2011
IS16.03.2012
Former [2012/20]LT16.11.2011
Documents cited:Search[YA]US5230039  (GROSSMAN MARK S [US], et al) [Y] 5,6,14,18 * column 11, line 16 - line 34 * * figure 3b * [A] 1-4,7-13,15-17,19,20;
 [XY]US6597363  (DULUK JR JEROME F [US], et al) [X] 1-4,7-13,15-17,19 * column 10, line 1 - line 4 * * column 35, line 55 - line 67 * [Y] 5,6,14,18,20;
 [YA]US6734861  (VAN DYKE JAMES M [US], et al) [Y] 5,6,14,18 * column 6, line 43 - line 51 * * column 7, line 36 - line 41 * * column 7, line 63 - line 65 * [A] 1-4,7-13,15-17,19,20;
 [YA]  - NAKATSUKA Y ET AL, "A one chip super graphics cpu with direct unified memory controller suitable for car information and control system", PROCEEDINGS OF THE IEEE 2001 CUSTOM INTEGRATED CIRCUITS CONFERENCE, SAN DIEGO, CA, NEW YORK, NY, (20010506), vol. 23, ISBN 978-0-7803-6591-9, pages 421 - 423, XP010546925 [Y] 20 * page 421; figure 2 * [A] 1-19

DOI:   http://dx.doi.org/10.1109/CICC.2001.929814
International search[Y]US6091857  (SHAW VENSON M [US], et al);
 [Y]US6597363  (DULUK JR JEROME F [US], et al)
Examination   - TORBORG J G, "A parallel processor architecture for graphics arithmetic operations", COMPUTER GRAPHICS, ACM, US, (19870701), vol. 21, no. 4, ISSN 0097-8930, pages 197 - 204, XP009130104
by applicantUS6597363
The EPO accepts no responsibility for the accuracy of data originating from other authorities; in particular, it does not guarantee that it is complete, up to date or fit for specific purposes.