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EP1815520

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EP About this file: EP1815520

EP1815520 - METHOD OF FORMING A SILICON-ON-INSULATOR SEMICONDUCTOR DEVICE WITH SILICON LAYER HAVING DEFFERENT CRYSTAL ORIENTATIONS [Right-click to bookmark this link]
Former [2007/32]	SILICON-ON-INSULATOR SEMICONDUCTOR DEVICE WITH SILICON LAYER HAVING DEFFERENT CRYSTAL ORIENTATIONS AND METHOD OF FORMING THE SILICON-ON-INSULATOR SEMICONDUCTOR DEVICE
	[2011/41]
Status	No opposition filed within time limit Status updated on 08.03.2013 Database last updated on 28.09.2024
Most recent event Tooltip	08.03.2013	No opposition filed within time limit	published on 10.04.2013 [2013/15]
Applicant(s)	For all designated states ADVANCED MICRO DEVICES, INC. One AMD Place Mail Stop 68 P.O. Box 3453 Sunnyvale CA 94088-3453 / US
	[2008/36]
Former [2007/32]	For all designated states ADVANCED MICRO DEVICES, INC. One AMD Place, Mail Stop 68, P.O.Box 9453 Sunnyvale, CA 94088-3453 / US
Inventor(s)	01 / WAITE, Andrew, M. 3603 Chelsea Cove South Hopewell Junction, NY 12533-6935 / US
	02 / CHEEK, Jon 2910 Kinloch Drive Cedar Park, TX 78613 / US
	[2007/38]
Former [2007/32]	01 / WAITE, Andrew, M. 3F Surrey Lane Wappingers Falls, NY 12590 / GB
	02 / CHEEK, Jon 2910 Kinloch Drive Cedar Park, TX 78613 / US
Representative(s)	Brookes IP Windsor House 6-10 Mount Ephraim Road Tunbridge Wells, Kent TN1 1EE / GB
	[N/P]
Former [2012/18]	Brookes Batchellor LLP 102-108 Clerkenwell Road London EC1M 5SA / GB
Former [2009/31]	Brookes Batchellor LLP 102-108 Clerkenwell Road London EC1M 5SA / GB
Former [2007/32]	Brookes Batchellor LLP 102-108 Clerkenwell Road London EC1M 5SA / GB
Application number, filing date	05812444.7	12.10.2005
	[2007/32]
	WO2005US36777
Priority number, date	US20040976780	01.11.2004 Original published format: US 976780
	[2007/32]
Filing language	EN
Procedural language	EN
Publication	Type:	A1 Application with search report
	No.:	WO2006049833
	Date:	11.05.2006
	Language:	EN
	[2006/19]
	Type:	A1 Application with search report
	No.:	EP1815520
	Date:	08.08.2007
	Language:	EN
	The application published by WIPO in one of the EPO official languages on 11.05.2006 takes the place of the publication of the European patent application.
	[2007/32]
	Type:	B1 Patent specification
	No.:	EP1815520
	Date:	02.05.2012
	Language:	EN
	[2012/18]
Search report(s)	International search report - published on:	EP	11.05.2006
Classification	IPC:	H01L21/336, H01L29/04, H01L29/786, H01L27/12, H01L21/84, H01L21/762	[2011/41]
	CPC:	H01L21/84 (EP,US); H01L27/12 (KR); H01L27/1203 (EP,US); H01L29/045 (EP,US); H01L29/66772 (EP,US); H01L29/78654 (EP,US)
	Former IPC [2007/32]	H01L27/12, H01L21/84, H01L21/762
Designated contracting states	DE, GB [2008/06]
Former [2007/32]	AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HU, IE, IS, IT, LI, LT, LU, LV, MC, NL, PL, PT, RO, SE, SI, SK, TR
Title	German:	VERFAHREN ZUR ERZEUGUNG EINES SILIZIUM-AUF-ISOLATOR-HALBLEITERBAUELEMENTS MIT EINER SILIZIUMSCHICHT MIT VERSCHIEDENEN KRISTALLORIENTIERUNGEN	[2011/41]
	English:	METHOD OF FORMING A SILICON-ON-INSULATOR SEMICONDUCTOR DEVICE WITH SILICON LAYER HAVING DEFFERENT CRYSTAL ORIENTATIONS	[2011/41]
	French:	PROCEDE DESTINE A FORMER UN DISPOSITIF A SEMI-CONDUCTEUR SILICIUM SUR ISOLANT AVEC COUCHE DE SILICIUM PRESENTANT DES ORIENTATIONS CRISTALLINES DIFFERENTES	[2011/41]
	Former [2007/32]	SILIZIUM-AUF-ISOLATOR-HALBLEITERBAUELEMENT MIT EINER SILIZIUMSCHICHT MIT VERSCHIEDENEN KRISTALLORIENTIERUNGEN UND VERFAHREN ZUR ERZEUGUNG DES SILIZIUM-AUF-ISOLATOR-HALBLEITERBAUELEMENTS
	Former [2007/32]	SILICON-ON-INSULATOR SEMICONDUCTOR DEVICE WITH SILICON LAYER HAVING DEFFERENT CRYSTAL ORIENTATIONS AND METHOD OF FORMING THE SILICON-ON-INSULATOR SEMICONDUCTOR DEVICE
	Former [2007/32]	DISPOSITIF A SEMI-CONDUCTEUR SILICIUM SUR ISOLANT AVEC COUCHE DE SILICIUM PRESENTANT DES ORIENTATIONS CRISTALLINES DIFFERENTES ET PROCEDE DESTINE A FORMER CE DISPOSITIF A SEMI-CONDUCTEUR SILICIUM SUR ISOLANT
Entry into regional phase	03.05.2007	National basic fee paid
	03.05.2007	Designation fee(s) paid
	03.05.2007	Examination fee paid
Examination procedure	31.08.2006	Request for preliminary examination filed International Preliminary Examining Authority: EP
	03.05.2007	Amendment by applicant (claims and/or description)
	03.05.2007	Examination requested [2007/32]
	31.05.2010	Despatch of a communication from the examining division (Time limit: M04)
	19.07.2010	Reply to a communication from the examining division
	10.12.2010	Date of oral proceedings
	19.01.2011	Minutes of oral proceedings despatched
	21.01.2011	Despatch of communication that the application is refused, reason: substantive examination {1}
	24.11.2011	Communication of intention to grant the patent
	21.03.2012	Fee for grant paid
	21.03.2012	Fee for publishing/printing paid
Appeal following examination	21.03.2011	Appeal received
	23.05.2011	Statement of grounds filed
	08.07.2011	Interlocutory revision of appeal
Divisional application(s)	The date of the Examining Division's first communication in respect of the earliest application for which a communication has been issued is 31.05.2010
Opposition(s)	05.02.2013	No opposition filed within time limit [2013/15]
Fees paid	Renewal fee
	03.05.2007	Renewal fee patent year 03
	27.03.2008	Renewal fee patent year 04
	07.10.2009	Renewal fee patent year 05
	23.09.2010	Renewal fee patent year 06
	10.10.2011	Renewal fee patent year 07
Opt-out from the exclusive Tooltip competence of the Unified Patent Court	See the Register of the Unified Patent Court for opt-out data
	Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court.
Cited in	International search	[PX]US6830962 (GUARINI KATHRYN W [US], et al) [PX] 1-10 * the whole document *;
		[PX]US6949420 (YAMASHITA TENKO [US]) [PX] 1-10 * the whole document *;
		[E]WO2005124871 (IBM [US], et al) [E] 1-4,6,7,10 * the whole document *;
		[PXA]WO2005057631 (IBM [US], et al) [PX] 1-5 * figures 5,6 * * figure 8 * [PA] 6-10;
		[X]US2004195646 (YEO YEE-CHIA [TW], et al) [X] 1-5 * abstract *;
		[X]EP0331811 (FUJITSU LTD [JP]) [X] 1-5 * abstract *;
		[A]JPS60154548 ;
		[A] - PATENT ABSTRACTS OF JAPAN, (19851217), vol. 009, no. 321, Database accession no. (E - 367), & JP60154548 A 19850814 (FUJITSU KK) [A] 1-5 * abstract *
		[A] - YANG M ET AL, "High Performance CMOS Fabricated on Hybrid Substrate With Different Crystal Orientations", INTERNATIONAL ELECTRON DEVICES MEETING 2003. IEDM. TECHNICAL DIGEST. WASHINGTON, DC, DEC 8 - 10, 2003, NEW YORK, NY : IEEE, US, (20031208), ISBN 0-7803-7872-5, pages 453 - 456, XP010684050 [A] 1-10 * abstract *

The EPO accepts no responsibility for the accuracy of data originating from other authorities; in particular, it does not guarantee that it is complete, up to date or fit for specific purposes.

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