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EP1808885
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EP About this file: EP1808885
| EP1808885 - A semiconductor device and method of fabricating a semiconductor device [Right-click to bookmark this link] | Status | The application has been withdrawn Status updated on 01.10.2010 Database last updated on 30.07.2024 | Most recent event Tooltip | 01.10.2010 | Withdrawal of application | published on 03.11.2010 [2010/44] | Applicant(s) | For all designated states Semequip, Inc. 34 Sullivan Road, Unit 21 Billerica Massachusetts, 01862 / US | [2007/29] | Inventor(s) | 01 /
Krull, Wade, A. 8 Smith Street Marblehead, MA 01945 / US | 02 /
Jacobson, Dale, C. 16 Flintlock Road Salem, NH 03079 / US | [2007/29] | Representative(s) | Paustian, Othmar Boeters & Lieck Patentanwälte Oberanger 32 80331 München / DE | [N/P] |
| Former [2007/29] | Paustian, Othmar BOETERS & LIECK Oberanger 32 80331 München / DE | Application number, filing date | 06020849.3 | 18.06.2003 | [2007/29] | Priority number, date | US20020392023P | 26.06.2002 Original published format: US 392023 P | US20020391802P | 26.06.2002 Original published format: US 391802 P | [2007/29] | Filing language | EN | Procedural language | EN | Publication | Type: | A1 Application with search report | No.: | EP1808885 | Date: | 18.07.2007 | Language: | EN | [2007/29] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 18.06.2007 | Classification | IPC: | H01L21/225, H01L21/265 | [2007/29] | CPC: |
H01L21/2255 (EP);
H01L21/265 (EP)
| Designated contracting states | AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HU, IE, IT, LI, LU, MC, NL, PT, RO, SE, SI, SK, TR [2007/29] | Title | German: | Halbleiterbauelement und Verfahren zur Herstellung eines Halbleiterbauelements | [2007/29] | English: | A semiconductor device and method of fabricating a semiconductor device | [2007/29] | French: | Dispositif semi-conducteur et son procédé de fabrication | [2007/29] | Examination procedure | 14.01.2008 | Examination requested [2008/09] | 22.02.2008 | Despatch of a communication from the examining division (Time limit: M06) | 09.10.2008 | Despatch of communication that the application is deemed to be withdrawn, reason: reply to the communication from the examining division not received in time | 07.11.2008 | Reply to a communication from the examining division | 05.10.2009 | Despatch of a communication from the examining division (Time limit: M06) | 15.04.2010 | Reply to a communication from the examining division | 24.09.2010 | Application withdrawn by applicant [2010/44] | Parent application(s) Tooltip | EP03761936.8 / EP1540720 | Divisional application(s) | The date of the Examining Division's first communication in respect of the earliest application for which a communication has been issued (EP20030761936) is 17.11.2009 | Request for further processing for: | The application is deemed to be withdrawn due to failure to reply to the examination report | 05.12.2008 | Request for further processing filed | 05.12.2008 | Full payment received (date of receipt of payment) | Fees paid | Renewal fee | 02.02.2007 | Renewal fee patent year 03 | 02.02.2007 | Renewal fee patent year 04 | 27.06.2007 | Renewal fee patent year 05 | 31.03.2008 | Renewal fee patent year 06 | 26.06.2009 | Renewal fee patent year 07 | Penalty fee | Additional fee for renewal fee | 30.06.2010 | 08 M06 Not yet paid |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [X]EP0219243 (MONOLITHIC MEMORIES INC [US]) [X] 1-4 * the whole document *; | [X]WO9965070 (KONINKL PHILIPS ELECTRONICS NV [NL], et al) [X] 1-4 * figures 1-6 *; | [A]EP1093149 (AXCELIS TECH INC [US]) [A] 1-4* the whole document *; | [X]WO0143175 (INFINEON TECHNOLOGIES CORP [US], et al) [X] 1-4 * abstract *; | [DX] - SCHMITZ J. ET AL, "Ultra-shallow junction formation by outdiffusion from implanted oxide", 195TH MEETING OF THE ELECTROCHEMICAL SOCIETY, Washington, (1998), pages 1009 - 1012, XP002434976 [DX] 1-4 * the whole document * DOI: http://dx.doi.org/10.1109/IEDM.1998.746525 | [DA] - FAIR R, "Physical models of boron diffusion in ultrathin gate oxides", JOURNAL OF THE ELECTROCHEMICAL SOCIETY, (199702), vol. 144, no. 2, pages 708 - 717, XP002434977 [DA] 3 * the whole document * DOI: http://dx.doi.org/10.1149/1.1837473 | Examination | US5817561 | by applicant | US6452338 | - M. KASE, "FEOL Technologies for Fabricating High Performance Logic and System LSI of 100nm node", 12TH INTERNATIONAL CONFERENCE ON ION IMPLANTATION TECHNOLOGY PROCEEDINGS, (1998), page 91 | - GHANI, SYMPOSIUM VLSI TECHNOLOGY, (2001), pages 17 - 18 | - SCHMITZ, "Ultra-Shallow Junction Formation by Outdiffusion from Implanted Oxide", IEEE - IEDM '98, page 1009 | - "Shallow Junction Fabrication by Rapid Thermal Outdiffusion from Implanted Oxides", SCHMITZ, PROCEEDINGS OF ADVANCES IN RAPID THERMAL PROCESSING, ELECTROCHEMICAL SOCIETY, (1999), page 187 | - FAIR, "Physical Models of Boron Diffusion in Ultrathin Gate Oxides", J. ELECTROCHEM. SOC, (1997), vol. 144, pages 708 - 717 | - KRULL, "The importance of the native oxide for sub-keV ion implants", PROC. 12TH INTERNATIONAL CONFERENCE ON ION IMPLANT TECHNOLOGY-1998, (1999), page 1113 |