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EP1753276
European procedure
Extract from the Register of European Patents
EP About this file: EP1753276
| EP1753276 - Method of soldering a quad flat package IC on a printed circuit board [Right-click to bookmark this link] | Status | No opposition filed within time limit Status updated on 25.02.2011 Database last updated on 03.10.2024 | Most recent event Tooltip | 25.02.2011 | No opposition filed within time limit | published on 30.03.2011 [2011/13] | Applicant(s) | For all designated states Mitsubishi Electric Corporation 7-3, Marunouchi 2-chome Chiyoda-ku Tokyo 100-8310 / JP | [N/P] |
| Former [2010/16] | For all designated states Mitsubishi Electric Corporation 7-3, Marunouchi 2-chome Chiyoda-ku Tokyo 100-8310 / JP | ||
| Former [2007/07] | For all designated states MITSUBISHI ELECTRIC CORPORATION 7-3, Marunouchi 2-chome Chiyoda-ku Tokyo Tokyo 100-8310 / JP | Inventor(s) | 01 /
Miura, Tsuyoshi c/o Mitsubishi Elec. Corporation 7-3, Marunouchi 2-chome Chiyoda-ku Tokyo 100-8310 / JP | [2007/07] | Representative(s) | Nicholls, Michael John J A Kemp 14 South Square Gray's Inn London WC1R 5JJ / GB | [N/P] |
| Former [2007/07] | Nicholls, Michael John J.A. KEMP & CO. 14, South Square Gray's Inn London WC1R 5JJ / GB | Application number, filing date | 06254143.8 | 08.08.2006 | [2007/07] | Priority number, date | JP20050230509 | 09.08.2005 Original published format: JP 2005230509 | [2007/07] | Filing language | EN | Procedural language | EN | Publication | Type: | A1 Application with search report | No.: | EP1753276 | Date: | 14.02.2007 | Language: | EN | [2007/07] | Type: | B1 Patent specification | No.: | EP1753276 | Date: | 21.04.2010 | Language: | EN | [2010/16] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 07.11.2006 | Classification | IPC: | H05K3/34 | [2007/07] | CPC: |
H05K3/3421 (EP,US);
H05K3/3468 (EP,US);
H05K2201/0969 (EP,US);
H05K2201/09781 (EP,US);
H05K2201/10689 (EP,US);
H05K2203/046 (EP,US);
Y02P70/50 (EP,US)
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| Designated contracting states | ES, GB, IT [2007/42] |
| Former [2007/07] | AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HU, IE, IS, IT, LI, LT, LU, LV, MC, NL, PL, PT, RO, SE, SI, SK, TR | Title | German: | Verfahren zum Löten einer integrierten Schaltung mit QFP Gehäuse auf einer Leiterplatte | [2007/07] | English: | Method of soldering a quad flat package IC on a printed circuit board | [2007/07] | French: | Procédé de brasage d'un circuit intégré en boîtier QFP sur un circuit imprimé | [2007/07] | Examination procedure | 08.12.2006 | Examination requested [2007/07] | 26.03.2007 | Despatch of a communication from the examining division (Time limit: M04) | 05.07.2007 | Reply to a communication from the examining division | 18.12.2007 | Despatch of a communication from the examining division (Time limit: M04) | 13.03.2008 | Reply to a communication from the examining division | 25.06.2009 | Date of oral proceedings | 23.09.2009 | Date of oral proceedings | 16.10.2009 | Minutes of oral proceedings despatched | 20.11.2009 | Communication of intention to grant the patent | 04.03.2010 | Fee for grant paid | 04.03.2010 | Fee for publishing/printing paid | Opposition(s) | 24.01.2011 | No opposition filed within time limit [2011/13] | Fees paid | Renewal fee | 20.03.2008 | Renewal fee patent year 03 | 12.08.2009 | Renewal fee patent year 04 |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [Y]DE3843191 (BROADCAST TELEVISION SYST [DE]) [Y] 7,8 * column 2, lines 19-57; figure 1 *; | [XY]JPH05315733 (SANYO ELECTRIC CO) [X] 1-6,9 * abstract * [Y] 7,8; | [X]JPH08250844 (OKI DATA KK) [X] 1,3-6 * abstract *; | [A]DE19541340 (LINDE AG [DE], et al) [A] 7* the whole document *; | [A]DE19609877 (LINDE AG [DE], et al) [A] 7 * column 2, lines 6-30; figure 1 * |