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EP1914795
European procedure
Extract from the Register of European Patents
EP About this file: EP1914795
| EP1914795 - Silicon wafer for semiconductor and manufacturing method thereof [Right-click to bookmark this link] | Status | No opposition filed within time limit Status updated on 24.09.2010 Database last updated on 19.10.2024 | Most recent event Tooltip | 24.09.2010 | No opposition filed within time limit | published on 27.10.2010 [2010/43] | Applicant(s) | For all designated states Siltronic AG Hanns-Seidel-Platz 4 81737 München / DE | [2008/17] | Inventor(s) | 01 /
Nakai, Katsuhiko, Dr. 2-3-34 Shinkai Murozumi Hikari Yamaguchi 743-0071 / JP | 02 /
von Ammon, Wilfried, Dr. Wanghausen 111 5122 Hochburg/Ach / AT | 03 /
Fukushima, Sei, Dr. B103, 3-14-45, Tsumada-Kita Atsugi Kanagawa 243-0812 / JP | 04 /
Schmidt, Herbert Thalhausen 12 84553 Halsbach / DE | 05 /
Weber, Martin, Dr. Forsterstrasse 8 84556 Kastl / DE | [2008/17] | Representative(s) | Baar, Christian, et al c/o Siltronic AG Corporate Intellectual Property Hanns-Seidel-Platz 4 81737 München / DE | [N/P] |
| Former [2008/17] | Baar, Christian, et al c/o Siltronic AG Corporate Intellectual Property Hanns-Seidel-Platz 4 81737 München / DE | Application number, filing date | 07017887.6 | 12.09.2007 | [2008/17] | Priority number, date | JP20070178920 | 06.07.2007 Original published format: JP 2007178920 | JP20060254946 | 20.09.2006 Original published format: JP 2006254946 | [2008/17] | Filing language | EN | Procedural language | EN | Publication | Type: | A1 Application with search report | No.: | EP1914795 | Date: | 23.04.2008 | Language: | EN | [2008/17] | Type: | B1 Patent specification | No.: | EP1914795 | Date: | 18.11.2009 | Language: | EN | [2009/47] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 20.12.2007 | Classification | IPC: | H01L21/322, C30B33/00, C30B29/06, // C30B15/20 | [2008/17] | CPC: |
H01L21/3225 (EP,US);
H01L21/302 (KR);
C30B15/206 (EP,US);
C30B29/06 (EP,US);
C30B33/00 (EP,US);
H01L21/20 (KR);
Y10T428/24992 (EP,US)
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| Designated contracting states | DE [2009/01] |
| Former [2008/17] | AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HU, IE, IS, IT, LI, LT, LU, LV, MC, MT, NL, PL, PT, RO, SE, SI, SK, TR | Title | German: | Siliciumwafer für Halbleiter und Verfahren zu seiner Herstellung | [2008/17] | English: | Silicon wafer for semiconductor and manufacturing method thereof | [2008/17] | French: | Tranche de silicium pour semi-conducteur et son procédé de fabrication | [2008/17] | Examination procedure | 12.09.2007 | Examination requested [2008/17] | 01.02.2008 | Despatch of a communication from the examining division (Time limit: M04) | 28.05.2008 | Reply to a communication from the examining division | 24.10.2008 | Loss of particular rights, legal effect: designated state(s) | 01.12.2008 | Despatch of communication of loss of particular rights: designated state(s) AT, BE, BG, CH, CY, CZ, DK, EE, ES, FI, FR, GB, GR, HU, IE, IS, IT, LT, LU, LV, MC, MT, NL, PL, PT, RO, SE, SI, SK, TR | 21.07.2009 | Communication of intention to grant the patent | 30.09.2009 | Fee for grant paid | 30.09.2009 | Fee for publishing/printing paid | Opposition(s) | 19.08.2010 | No opposition filed within time limit [2010/43] | Fees paid | Renewal fee | 23.09.2009 | Renewal fee patent year 03 |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [DY]JP2006040980 (SUMCO CORP) [DY] 1-3 * abstract * * table I *; | [Y]US5502331 (INOUE YOKO [JP], et al) [Y] 1-3 * abstract *; | [DY]JP2000281491 (NIPPON STEEL CORP) [DY] 2,3 * abstract * |