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EP1819055
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EP About this file: EP1819055
| EP1819055 - Multi-rate low density parity check (LDPC) decoder and decoding method [Right-click to bookmark this link] | Status | The application has been withdrawn Status updated on 23.04.2010 Database last updated on 19.10.2024 | Most recent event Tooltip | 23.04.2010 | Withdrawal of application | published on 26.05.2010 [2010/21] | Applicant(s) | For all designated states Fujitsu Ltd. 1-1, Kamikodanaka 4-chome, Nakahara-ku Kawasaki-shi, Kanagawa 211-8588 / JP | [2007/33] | Inventor(s) | 01 /
Ikeda, Norihiro c/o FUJITSU LIMITED 1-1, Kamikodanaka 4-chome Nakahara-ku Kawasaki-shi Kanagawa 211-8588 / JP | 02 /
Miyazaki, Shunji c/o FUJITSU LIMITED 1-1, Kamikodanaka 4-chome Nakahara-ku Kawasaki-shi Kanagawa 211-8588 / JP | [2007/33] | Representative(s) | Stebbing, Timothy Charles Haseltine Lake LLP Lincoln House, 5th Floor 300 High Holborn London WC1V 7JH / GB | [N/P] |
| Former [2007/33] | Stebbing, Timothy Charles Haseltine Lake Lincoln House 300 High Holborn London WC1V 7JH / GB | Application number, filing date | 07101974.9 | 08.02.2007 | [2007/33] | Priority number, date | JP20060035019 | 13.02.2006 Original published format: JP 2006035019 | [2007/33] | Filing language | EN | Procedural language | EN | Publication | Type: | A1 Application with search report | No.: | EP1819055 | Date: | 15.08.2007 | Language: | EN | [2007/33] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 01.06.2007 | Classification | IPC: | H03M13/11 | [2007/33] | CPC: |
H03M13/1137 (EP,US);
H03M13/033 (EP,US);
H03M13/1111 (EP,US);
H03M13/6516 (EP,US)
| Designated contracting states | DE, FR, GB, IT [2008/17] |
| Former [2007/33] | AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HU, IE, IS, IT, LI, LT, LU, LV, MC, NL, PL, PT, RO, SE, SI, SK, TR | Title | German: | Low density parity check (LDPC) Decodierer und Decodiermethode für verschiedene Raten | [2007/33] | English: | Multi-rate low density parity check (LDPC) decoder and decoding method | [2007/33] | French: | Dispositif et procédé décodeur de codes LDPC à plusieurs débits | [2007/33] | Examination procedure | 04.02.2008 | Amendment by applicant (claims and/or description) | 11.02.2008 | Examination requested [2008/13] | 16.02.2008 | Loss of particular rights, legal effect: designated state(s) | 25.03.2008 | Despatch of communication of loss of particular rights: designated state(s) AT, BE, BG, CH, CY, CZ, DK, EE, ES, FI, GR, HU, IE, IS, LT, LU, LV, MC, NL, PL, PT, RO, SE, SI, SK, TR | 09.04.2010 | Application withdrawn by applicant [2010/21] | Fees paid | Renewal fee | 17.03.2008 | Renewal fee patent year 03 | 25.02.2010 | Renewal fee patent year 04 |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [A]EP1610466 (INFINEON TECHNOLOGIES AG [DE]) [A] 1-8 * paragraphs [0107] , [0114] , [0115] , [0126]; figures 17,21,23 *; | [A]WO2006001015 (RUNCOM TECHNOLOGIES LTD [IL], et al) [A] 1-8 * page 4 - page 11; figure 7 *; | [A] - ROVINI M ET AL, "VLSI Design of a High-Throughput Multi-Rate Decoder for Structured LDPC Codes", PROC., IEEE EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN, PORTO, PORTUGAL, (20050830), ISBN 0-7695-2433-8, pages 202 - 209, XP010864680 [A] 1-8 * page 203 - page 205 * * page 207, column L * DOI: http://dx.doi.org/10.1109/DSD.2005.77 | [A] - SHASHA E ET AL, "Multi-Rate LDPC code for OFDMA PHY", INTERNET CITATION, (20040627), URL: http://www.ieee802.org/16/tge/contrib/C80216e-04_185.pdf, (20050705), XP002334837 [A] 1-8 * page 1 - page 4 * | [A] - EROZ M ET AL, "Structured Low-Density Parity-Check Code Design for Next Generation Digital Video Broadcast", PROC., IEEE CONFERENCE ON MILITARY COMMUNICATIONS, MILCOM 2005, ATLANTIC CITY, NJ, USA, (20051017), ISBN 0-7803-9393-7, pages 1 - 6, XP010901536 [A] 1-8 * the whole document * DOI: http://dx.doi.org/10.1109/MILCOM.2005.1606037 | [A] - VILA CASADO A I ET AL, "Multiple rate low-density parity-check codes with constant blocklength", PROC., IEEE ASIMOLAR CONFERENCE ON SIGNALS, SYSTEMS AND COMPUTERS, PACIFIC GROVE, CA, USA, (20041107), ISBN 0-7803-8622-1, pages 2010 - 2014, XP010781157 [A] 1-8 * the whole document * DOI: http://dx.doi.org/10.1109/ACSSC.2004.1399517 | [A] - SHIMIZU K ET AL, "Partially-Parallel LDPC Decoder Based on High-Efficiency Message-Passing Algorithm", PROC., IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN, SAN JOSE, CA, USA, (20051002), ISBN 0-7695-2451-6, pages 503 - 510, XP010846468 [A] 1-8 * the whole document * | [A] - LEI YANG ET AL, "An FPGA implementation of low-density parity-check code decoder with multi-rate capability", PROC., IEEE ASIA AND SOUTH PACIFIC AUTOMATION CONFERENCE, ASP-DAC 2005, SHANGHAI, CHINA, (20050118), ISBN 0-7803-8736-8, pages 760 - 763, XP010814461 [A] 1-8 * page 761 - page 763 * | by applicant | EP1610466 | WO2006001015 |