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EP1833090
European procedure
Extract from the Register of European Patents
EP About this file: EP1833090
| EP1833090 - Memory cells in double-gate CMOS technology fitted with independent double-gate transistors [Right-click to bookmark this link] | |||
| Former [2007/37] | Memory cells in double-gate CMOS technology fitted with transistors with independent double-gate transistors | ||
| [2012/46] | Status | No opposition filed within time limit Status updated on 07.02.2014 Database last updated on 29.06.2024 | Most recent event Tooltip | 07.02.2014 | Lapse of the patent in a contracting state | published on 12.03.2014 [2014/11] | 07.02.2014 | No opposition filed within time limit | published on 12.03.2014 [2014/11] | Applicant(s) | For all designated states Commissariat à l'Énergie Atomique et aux Énergies Alternatives Bâtiment "Le Ponant D" 25, rue Leblanc 75015 Paris / FR | [2013/14] |
| Former [2010/18] | For all designated states Commissariat à l'énergie atomique et aux énergies alternatives Bâtiment D "Le Ponant" 25, rue Leblanc 75015 Paris / FR | ||
| Former [2007/37] | For all designated states COMMISSARIAT A L'ENERGIE ATOMIQUE 25, rue Leblanc Immeuble "Le Ponant D" 75015 Paris / FR | Inventor(s) | 01 /
Thomas, Olivier Les Faures 38420 Revel / FR | 02 /
Belleville, Marc 12 rue de Chantemerle 38120 Saint-Egreve / FR | [2007/37] | Representative(s) | Ahner, Philippe, et al Brevalex Tour Trinity 1 Bis Esplanade de La Défense CS 60347 92035 Paris La Défense Cedex / FR | [N/P] |
| Former [2013/13] | Ahner, Philippe, et al BREVALEX 95 rue d'Amsterdam 75378 Paris Cedex 8 / FR | ||
| Former [2010/34] | Poulin, Gérard, et al BREVALEX 3, rue du Docteur Lancereaux 75008 Paris / FR | ||
| Former [2010/34] | Poulin, Gérard, et al BREVALEX 3, rue du Docteur Lancereaux 75008 Paris / FR | ||
| Former [2010/34] | Poulin, Gérard, et al Brevatome 3, rue du Docteur Lancereaux 75008 Paris / FR | ||
| Former [2007/37] | Poulin, Gérard, et al Société BREVATOME 3, rue du Docteur Lancereaux 75008 Paris / FR | Application number, filing date | 07103731.1 | 08.03.2007 | [2007/37] | Priority number, date | FR20060050824 | 10.03.2006 Original published format: FR 0650824 | [2007/37] | Filing language | FR | Procedural language | FR | Publication | Type: | A2 Application without search report | No.: | EP1833090 | Date: | 12.09.2007 | Language: | FR | [2007/37] | Type: | A3 Search report | No.: | EP1833090 | Date: | 14.11.2007 | [2007/46] | Type: | B1 Patent specification | No.: | EP1833090 | Date: | 03.04.2013 | Language: | FR | [2013/14] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 16.10.2007 | Classification | IPC: | H01L27/11 | [2007/37] | CPC: |
G11C11/412 (EP,US);
H10B10/12 (EP,US)
| Designated contracting states | DE, GB, IT [2008/30] |
| Former [2007/37] | AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HU, IE, IS, IT, LI, LT, LU, LV, MC, MT, NL, PL, PT, RO, SE, SI, SK, TR | Title | German: | Speicherzellen der CMOS-Technologie mit Doppel-Gate, die mit Transistoren mit zwei unabhängigen Gates ausgestattet sind | [2007/37] | English: | Memory cells in double-gate CMOS technology fitted with independent double-gate transistors | [2012/46] | French: | Cellules mémoire en technologie CMOS double-grille dotée de transistors à deux grilles independantes | [2007/37] |
| Former [2007/37] | Memory cells in double-gate CMOS technology fitted with transistors with independent double-gate transistors | Examination procedure | 02.05.2008 | Examination requested [2008/24] | 15.05.2008 | Loss of particular rights, legal effect: designated state(s) | 20.06.2008 | Despatch of communication of loss of particular rights: designated state(s) AT, BE, BG, CH, CY, CZ, DK, EE, ES, FI, FR, GR, HU, IE, IS, LT, LU, LV, MC, MT, NL, PL, PT, RO, SE, SI, SK, TR | 23.11.2010 | Despatch of a communication from the examining division (Time limit: M06) | 01.04.2011 | Reply to a communication from the examining division | 23.10.2012 | Communication of intention to grant the patent | 29.01.2013 | Fee for grant paid | 29.01.2013 | Fee for publishing/printing paid | Divisional application(s) | The date of the Examining Division's first communication in respect of the earliest application for which a communication has been issued is 23.11.2010 | Opposition(s) | 06.01.2014 | No opposition filed within time limit [2014/11] | Fees paid | Renewal fee | 23.03.2009 | Renewal fee patent year 03 | 26.03.2010 | Renewal fee patent year 04 | 24.03.2011 | Renewal fee patent year 05 | 22.02.2012 | Renewal fee patent year 06 | 21.02.2013 | Renewal fee patent year 07 |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Lapses during opposition Tooltip | IT | 03.04.2013 | [2014/11] | Documents cited: | Search | [A] - KIYOSHI TAKEUCHI ET AL, "A Study of the Threshold Voltage Variation for Ultra-Small Bulk and SOI CMOS", IEEE TRANSACTIONS ON ELECTRON DEVICES, IEEE SERVICE CENTER, PISACATAWAY, NJ, US, (200109), vol. 48, no. 9, ISSN 0018-9383, XP011017796 [A] 1-10 * abstract * | [A] - ANANTHAN H ET AL, "FinFET SRAM-device and circuit design considerations", QUALITY ELECTRONIC DESIGN, 2004. PROCEEDINGS. 5TH INTERNATIONAL SYMPOSIUM ON SAN JOSE, CALIFORNIA 22-24 MARCH 2004, PISCATAWAY, NJ, USA,IEEE, (20040322), ISBN 0-7695-2093-6, pages 511 - 516, XP010695543 [A] 1-10 * page 511; figures 1,6 * DOI: http://dx.doi.org/10.1109/ISQED.2004.1283724 | [A] - MAEGAWA S ET AL, "A 0.4 MUM GATE-ALL-AROUND TFT (GAT) USING A DUMMY NITRIDE PATTERN FOR HIGH-DENSITY MEMORIES", JAPANESE JOURNAL OF APPLIED PHYSICS, JAPAN SOCIETY OF APPLIED PHYSICS, TOKYO, JP, (19950201), vol. 34, no. 2B, PART 1, ISSN 0021-4922, pages 895 - 899, XP000599414 [A] 1-10 * page 895; figures 1-5 * DOI: http://dx.doi.org/10.1143/JJAP.34.895 | Examination | US2005199964 |