blank Quick help
blank Maintenance news

Scheduled maintenance

Regular maintenance outages:
between 05.00 and 05.15 hrs CET (Monday to Sunday).

Other outages
Availability

2022.02.11

More...
blank News flashes

News Flashes

New version of the European Patent Register – SPC proceedings information in the Unitary Patent Register.

2024-07-24

More...
blank Related links

Extract from the Register of European Patents

EP About this file: EP1930824

EP1930824 - CAD apparatus, method and computer product for designing printed circuit board [Right-click to bookmark this link]
StatusThe application has been refused
Status updated on  14.04.2017
Database last updated on 03.10.2024
Most recent event   Tooltip14.04.2017Refusal of applicationpublished on 17.05.2017  [2017/20]
Applicant(s)For all designated states
FUJITSU LIMITED
1-1, Kamikodanaka 4-chome, Nakahara-ku
Kawasaki-shi, Kanagawa 211-8588 / JP
[2008/24]
Inventor(s)01 / Kumagai, Yoshitomo
c/o FUJITSU LIMITED 1-1, Kamikodanaka 4-Chome Nakahara-ku
Kawasaki-shi, Kanagawa 211-8588 / JP
 [2008/24]
Representative(s)Kreutzer, Ulrich, et al
Cabinet Beau de Loménie
Lessingstrasse 6
80336 München / DE
[N/P]
Former [2008/39]Kreutzer, Ulrich, et al
Cabinet Beau de Loménie Bavariaring 26
80336 München / DE
Former [2008/24]Kreutzer, Ulrich, et al
Cabinet Beau de Loménie Bavariaring 26
80336 München / DE
Application number, filing date07117419.727.09.2007
[2008/24]
Priority number, dateJP2006033050107.12.2006         Original published format: JP 2006330501
[2008/24]
Filing languageEN
Procedural languageEN
PublicationType: A1 Application with search report 
No.:EP1930824
Date:11.06.2008
Language:EN
[2008/24]
Search report(s)(Supplementary) European search report - dispatched on:EP13.02.2008
ClassificationIPC:G06F17/50, G06T11/20
[2008/24]
CPC:
G06F30/18 (EP,US); G06F30/12 (US); G06F30/39 (EP,US);
G06F2115/12 (US)
Designated contracting statesDE,   FR [2009/08]
Former [2008/24]AT,  BE,  BG,  CH,  CY,  CZ,  DE,  DK,  EE,  ES,  FI,  FR,  GB,  GR,  HU,  IE,  IS,  IT,  LI,  LT,  LU,  LV,  MC,  MT,  NL,  PL,  PT,  RO,  SE,  SI,  SK,  TR 
TitleGerman:CAD-Vorrichtung und -Verfahren sowie Computerprogramm zum Entwerfen einer bestückten Leiterplatte[2008/24]
English:CAD apparatus, method and computer product for designing printed circuit board[2008/24]
French:Appareil de CAO et produit informatique pour la création d'une carte de circuit imprimé[2008/24]
Examination procedure22.09.2008Amendment by applicant (claims and/or description)
22.09.2008Examination requested  [2008/45]
12.12.2008Loss of particular rights, legal effect: designated state(s)
15.01.2009Despatch of communication of loss of particular rights: designated state(s) AT, BE, BG, CH, CY, CZ, DK, EE, ES, FI, GB, GR, HU, IE, IS, IT, LT, LU, LV, MC, MT, NL, PL, PT, RO, SE, SI, SK, TR
06.11.2009Despatch of a communication from the examining division (Time limit: M04)
16.03.2010Reply to a communication from the examining division
16.12.2016Application refused, date of legal effect [2017/20]
16.12.2016Date of oral proceedings
02.01.2017Despatch of communication that the application is refused, reason: substantive examination [2017/20]
02.01.2017Minutes of oral proceedings despatched
Divisional application(s)The date of the Examining Division's first communication in respect of the earliest application for which a communication has been issued is  06.11.2009
Fees paidRenewal fee
18.08.2009Renewal fee patent year 03
19.08.2010Renewal fee patent year 04
11.08.2011Renewal fee patent year 05
16.07.2012Renewal fee patent year 06
02.08.2013Renewal fee patent year 07
08.07.2014Renewal fee patent year 08
08.07.2015Renewal fee patent year 09
17.08.2016Renewal fee patent year 10
Opt-out from the exclusive  Tooltip
competence of the Unified
Patent Court
See the Register of the Unified Patent Court for opt-out data
Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court.
Documents cited:Search[A]US5164908  (IGARASHI SHINICHI [JP]) [A] 1-9 * abstract * * column 3 *;
 [X]US5568397  (YAMASHITA KEIICHIROU [JP], et al) [X] 1-9 * abstract * * column 4, line 9 - column 6, line 24 *;
 [X]US5987458  (ANDERSON KENNETH GEORGE [US], et al) [X] 1-9 * abstract * * column 6, line 26 - column 9, line 34 *;
 [X]US2002018583  (GONT VAL [CA], et al) [X] 1-9 * paragraph [0031] - paragraph [0033] * * paragraph [0055] - paragraph [0056] * * paragraph [0081] - paragraph [0082] *;
 [A]US2005080502  (CHERNYAK ALEX H [US], et al) [A] 1-9 * abstract * * paragraph [0061] - paragraph [0062] ** paragraph [0122] *;
 [X]  - HERNITER M E, "PC board design and fabrication using Schematics, PADS-PERFORM, and a laser printer", FRONTIERS IN EDUCATION CONFERENCE, 1994. TWENTY-FOURTH ANNUAL CONFERENCE. PROCEEDINGS SAN JOSE, CA, USA 2-6 NOV. 1994, NEW YORK, NY, USA,IEEE, (19941102), ISBN 0-7803-2413-7, pages 111 - 115, XP010218070 [X] 1-9 * page 111 - page 112 *

DOI:   http://dx.doi.org/10.1109/FIE.1994.580481
ExaminationUS2004034842
The EPO accepts no responsibility for the accuracy of data originating from other authorities; in particular, it does not guarantee that it is complete, up to date or fit for specific purposes.