EP2058848 - LATERAL JUNCTION FIELD EFFECT TRANSISTOR [Right-click to bookmark this link] | Status | The application has been refused Status updated on 25.09.2015 Database last updated on 24.07.2024 | Most recent event Tooltip | 25.09.2015 | Refusal of application | published on 28.10.2015 [2015/44] | Applicant(s) | For all designated states Sumitomo Electric Industries, Ltd. 5-33 Kitahama 4-chome Chuo-ku Osaka-shi Osaka 541-0041 / JP | [2009/20] | Inventor(s) | 01 /
MASUDA, Takeyoshi Osaka Works of SUMITOMO ELECTRIC INDUSTRIES LTD. 1-3 Shimaya 1-chome Konohana-ku Osaka-shi Osaka 554-0024 / JP | 02 /
NAMIKAWA, Yasuo Osaka Works of SUMITOMO ELECTRIC INDUSTRIES LTD. 1-3 Shimaya 1-chome Konohana-ku Osaka-shi Osaka 554-0024 / JP | [2009/20] | Representative(s) | Grünecker Patent- und Rechtsanwälte PartG mbB Leopoldstrasse 4 80802 München / DE | [N/P] |
Former [2009/20] | Grünecker, Kinkeldey, Stockmair & Schwanhäusser Anwaltssozietät Leopoldstrasse 4 80802 München / DE | Application number, filing date | 07807695.7 | 21.09.2007 | [2009/20] | WO2007JP68345 | Priority number, date | JP20060340137 | 18.12.2006 Original published format: JP 2006340137 | [2009/20] | Filing language | JA | Procedural language | EN | Publication | Type: | A1 Application with search report | No.: | WO2008075488 | Date: | 26.06.2008 | Language: | JA | [2008/26] | Type: | A1 Application with search report | No.: | EP2058848 | Date: | 13.05.2009 | Language: | EN | [2009/20] | Search report(s) | International search report - published on: | JP | 26.06.2008 | (Supplementary) European search report - dispatched on: | EP | 15.12.2010 | Classification | IPC: | H01L21/337, H01L29/417, H01L29/808 | [2009/20] | CPC: |
H01L29/808 (EP,US);
H01L29/735 (KR);
H01L21/048 (EP,US);
H01L29/1066 (EP,US);
H01L29/66901 (EP,US);
H01L29/1608 (EP,US);
H01L29/2003 (EP,US)
(-)
| Designated contracting states | AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HU, IE, IS, IT, LI, LT, LU, LV, MC, MT, NL, PL, PT, RO, SE, SI, SK, TR [2009/20] | Title | German: | FELDEFFEKTTRANSISTOR MIT SEITLICHEM ANSCHLUSS | [2009/20] | English: | LATERAL JUNCTION FIELD EFFECT TRANSISTOR | [2009/20] | French: | TRANSISTOR A EFFET DE CHAMP A JONCTION LATERALE | [2009/20] | Entry into regional phase | 06.02.2009 | Translation filed | 06.02.2009 | National basic fee paid | 06.02.2009 | Search fee paid | 06.02.2009 | Designation fee(s) paid | 06.02.2009 | Examination fee paid | Examination procedure | 06.02.2009 | Examination requested [2009/20] | 13.07.2011 | Amendment by applicant (claims and/or description) | 25.04.2013 | Despatch of a communication from the examining division (Time limit: M04) | 18.06.2013 | Reply to a communication from the examining division | 20.05.2015 | Cancellation of oral proceeding that was planned for 01.12.2015 | 08.06.2015 | Despatch of communication that the application is refused, reason: substantive examination [2015/44] | 18.06.2015 | Application refused, date of legal effect [2015/44] | 01.12.2015 | Date of oral proceedings (cancelled) | Divisional application(s) | The date of the Examining Division's first communication in respect of the earliest application for which a communication has been issued is 25.04.2013 | Fees paid | Renewal fee | 29.09.2009 | Renewal fee patent year 03 | 29.09.2010 | Renewal fee patent year 04 | 28.09.2011 | Renewal fee patent year 05 | 27.09.2012 | Renewal fee patent year 06 | 26.09.2013 | Renewal fee patent year 07 | 26.09.2014 | Renewal fee patent year 08 |
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Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [X]EP0268426 (LINEAR TECHN INC [US]) [X] 1-5* column 3; figure 3 *; | [X]US5319227 (LAPHAM JEROME F [US], et al) [X] 1-5 * columns 3,4; figures 1,2 *; | [XD]JP2003068762 (SUMITOMO ELECTRIC INDUSTRIES) [XD] 1,2,4,5 * figure 2 * | International search | [X]JPS61101082 (HITACHI LTD); | [X]JPH01243475 (HITACHI LTD); | [Y]WO2004112150 (SUMITOMO ELECTRIC INDUSTRIES [JP], et al); | [Y]JP2003068762 (SUMITOMO ELECTRIC INDUSTRIES) | Examination | - NANVER L K ET AL, "DESIGN CONSIDERATIONS FOR INTEGRATED HIGH-FREQUENCY P-CHANNEL JFET'S", IEEE TRANSACTIONS ON ELECTRON DEVICES, IEEE SERVICE CENTER, PISACATAWAY, NJ, US, (19881101), vol. 35, no. 11, doi:10.1109/16.7406, ISSN 0018-9383, pages 1924 - 1934, XP000070048 DOI: http://dx.doi.org/10.1109/16.7406 | by applicant | JP2003068762 |