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EP2153460
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EP About this file: EP2153460
| EP2153460 - PAD LAYOUT STRUCTURE OF SEMICONDUCTOR CHIP [Right-click to bookmark this link] | Status | The application is deemed to be withdrawn Status updated on 19.08.2016 Database last updated on 14.09.2024 | Most recent event Tooltip | 19.08.2016 | Application deemed to be withdrawn | published on 21.09.2016 [2016/38] | Applicant(s) | For all designated states Silicon Works Co., Ltd. 104-13, Munji-dong Yuseong-gu Daejeon-si 305-380 / KR | [2010/07] | Inventor(s) | 01 /
HAN, Dae Keun 109-1301 Hyangchon Apt 970 Dunsan-dong Seo-gu Daejeon-si 302-120 / KR | 02 /
KIM, Dae Seong 6-1503 Shindong-a Apt. Ojeong-dong Daedeok-gu Daejeon-si 306-787 / KR | 03 /
NA, Joon Ho 8-608 Sujeong Apt. Dunsan 2-dong Seo-gu Daejeon-si 302-120 / KR | [2010/07] | Representative(s) | Neobard, William John, et al Kilburn & Strode LLP Lacon London 84 Theobalds Road London WC1X 8NL / GB | [N/P] |
| Former [2010/07] | Neobard, William John, et al Kilburn & Strode LLP 20 Red Lion Street London WC1R 4PJ / GB | Application number, filing date | 07851544.2 | 17.12.2007 | [2010/07] | WO2007KR06573 | Priority number, date | KR20070055311 | 07.06.2007 Original published format: KR 20070055311 | [2010/07] | Filing language | EN | Procedural language | EN | Publication | Type: | A1 Application with search report | No.: | WO2008150055 | Date: | 11.12.2008 | Language: | EN | [2008/50] | Type: | A1 Application with search report | No.: | EP2153460 | Date: | 17.02.2010 | Language: | EN | The application published by WIPO in one of the EPO official languages on 11.12.2008 takes the place of the publication of the European patent application. | [2010/07] | Search report(s) | International search report - published on: | KR | 11.12.2008 | (Supplementary) European search report - dispatched on: | EP | 04.04.2014 | Classification | IPC: | H01L21/60, H01L23/544, H01L23/48 | [2014/19] | CPC: |
H01L24/06 (EP,US);
H01L23/544 (EP,US);
H01L2223/54426 (EP,US);
H01L2224/05553 (EP,US);
H01L2224/05599 (EP,US);
H01L2224/0603 (EP,US);
H01L2224/06051 (EP,US);
H01L2224/45144 (EP,US);
H01L2224/85399 (EP,US);
H01L2924/00014 (EP,US);
H01L2924/01005 (EP,US);
H01L2924/01006 (EP,US);
| C-Set: |
H01L2224/85399, H01L2924/00014 (EP,US);
H01L2924/00014, H01L2224/05599 (US,EP);
H01L2924/00014, H01L2224/48 (US,EP)
|
| Former IPC [2010/07] | H01L21/60 | Designated contracting states | AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HU, IE, IS, IT, LI, LT, LU, LV, MC, MT, NL, PL, PT, RO, SE, SI, SK, TR [2010/07] | Title | German: | PAD-LAYOUT-STRUKTUR EINES HALBLEITERCHIPS | [2010/07] | English: | PAD LAYOUT STRUCTURE OF SEMICONDUCTOR CHIP | [2010/07] | French: | STRUCTURE DE CONFIGURATION DES PLOTS D'UNE PUCE SEMI-CONDUCTRICE | [2010/07] | Entry into regional phase | 19.11.2009 | National basic fee paid | 19.11.2009 | Search fee paid | 19.11.2009 | Designation fee(s) paid | 19.11.2009 | Examination fee paid | Examination procedure | 19.11.2009 | Examination requested [2010/07] | 04.11.2014 | Amendment by applicant (claims and/or description) | 13.10.2015 | Despatch of a communication from the examining division (Time limit: M06) | 26.04.2016 | Application deemed to be withdrawn, date of legal effect [2016/38] | 19.05.2016 | Despatch of communication that the application is deemed to be withdrawn, reason: reply to the communication from the examining division not received in time [2016/38] | Divisional application(s) | The date of the Examining Division's first communication in respect of the earliest application for which a communication has been issued is 13.10.2015 | Fees paid | Renewal fee | 19.11.2009 | Renewal fee patent year 03 | 15.12.2010 | Renewal fee patent year 04 | 12.12.2011 | Renewal fee patent year 05 | 11.12.2012 | Renewal fee patent year 06 | 12.12.2013 | Renewal fee patent year 07 | 11.12.2014 | Renewal fee patent year 08 | 10.12.2015 | Renewal fee patent year 09 |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [I]JPH03190238 (MATSUSHITA ELECTRIC IND CO LTD) [I] 1-3,17 * abstract * * figure 1 *; | [A]US2003202150 (LEE SUNG-HO [KR]) [A] 1-3,17 * the whole document *; | [A]JP2004103751 (RENESAS TECH CORP) [A] 17 * abstract * * figure 1 * * paragraph [0021] *; | [XAI]WO2005088702 (MATSUSHITA ELECTRIC IND CO LTD [JP], et al) [X] 1,3 * figure 1 * * paragraphs [0025] - [0026] * [A] 2 [I] 17; | [A]US2005242436 (ABE HIDEAKI [JP], et al) [A] 17 * figures 6-11 * * paragraphs [0065] - [0084] *; | [A]US2006113648 (CHUNG YE-CHUNG [KR], et al) [A] 1-3,17 * figures 1, 2 *; | [A]US2007080416 (YOSHIOKA AKIHIKO [JP], et al) [A] 1-3,17 * figure 1 ** paragraphs [0047] - [0049] *; | US2008308798 [ ] (KOMATSU SHIGEYUKI [JP]) [ ] * figure 1 * * paragraphs [0185] - [0188] *; | [XAI] - "NOVEL FOOTPRINT DESIGN FOR TAB ASSEMBLY", IBM TECHNICAL DISCLOSURE BULLETIN, INTERNATIONAL BUSINESS MACHINES CORP. (THORNWOOD), US, (19920301), vol. 34, no. 10A, ISSN 0018-8689, pages 331 - 332, XP000302321 [X] 1,3 * the whole document * [A] 2 [I] 17 | International search | [A]JPS6072238 (TOSHIBA KK); | [A]JPS60101938 (NIPPON ELECTRIC CO); | [A]JPS60206158 (MATSUSHITA ELECTRIC IND CO LTD) |