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EP2104138
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EP About this file: EP2104138
| EP2104138 - Method for bonding chips onto a wafer [Right-click to bookmark this link] | Status | The application has been refused Status updated on 05.05.2017 Database last updated on 14.03.2026 | Most recent event Tooltip | 09.05.2017 | New entry: Additional fee for renewal fee: despatch of communication + time limit | Applicant(s) | For all designated states EV Group E. Thallner GmbH DI Erich Thallner Strasse 1 4782 St. Florian / AT | [2009/39] | Inventor(s) | 01 /
Wimplinger, Markus Braunauerstrasse 84 4910 Ried Im Innkreis / AT | [2009/39] | Representative(s) | Schweiger, Johannes, et al Becker & Müller Patentanwälte Turmstr. 22 40878 Ratingen / DE | [N/P] |
| Former [2009/39] | Schweiger, Johannes, et al Patentanwälte Becker & Müller Turmstrasse 22 D-40878 Ratingen / DE | Application number, filing date | 08005016.4 | 18.03.2008 | [2009/39] | Filing language | DE | Procedural language | DE | Publication | Type: | A1 Application with search report | No.: | EP2104138 | Date: | 23.09.2009 | Language: | DE | [2009/39] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 27.08.2008 | Classification | IPC: | H01L21/98, H01L21/68 | [2009/39] | CPC: |
H10P72/74 (EP,US);
B62H3/04 (EP,US);
H10P72/7402 (EP,US);
H10W90/00 (EP,US);
H10P72/7418 (EP,US);
H10W72/016 (EP,US);
H10W72/0198 (EP,US);
H10W72/072 (EP,US);
H10W72/07207 (EP,US);
H10W72/07236 (EP,US);
H10W72/07254 (EP,US);
H10W72/075 (EP,US);
H10W72/221 (EP,US);
H10W72/227 (EP,US);
H10W72/244 (EP,US);
H10W72/247 (EP,US);
H10W72/248 (EP,US);
H10W72/29 (EP,US);
H10W72/59 (EP,US);
H10W72/859 (EP,US);
H10W72/942 (EP,US);
H10W74/117 (EP,US);
H10W90/297 (EP,US);
H10W90/722 (EP,US);
| Designated contracting states | AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LI, LT, LU, LV, MC, MT, NL, NO, PL, PT, RO, SE, SI, SK, TR [2009/39] | Title | German: | Verfahren zum Bonden von Chips auf Wafer | [2009/39] | English: | Method for bonding chips onto a wafer | [2009/39] | French: | Procédé de liaison de puces sur une tranche semi-conductrice | [2009/39] | Examination procedure | 16.03.2010 | Examination requested [2010/17] | 12.04.2010 | Despatch of a communication from the examining division (Time limit: M04) | 17.06.2010 | Reply to a communication from the examining division | 01.02.2011 | Date of oral proceedings | 14.02.2011 | Minutes of oral proceedings despatched | 15.02.2011 | Despatch of communication that the application is refused, reason: substantive examination [2017/23] | 08.04.2017 | Application refused, date of legal effect [2017/23] | Appeal following examination | 06.04.2011 | Appeal received No. T1816/11 | 10.06.2011 | Statement of grounds filed | 22.11.2016 | Result of appeal procedure: appeal of the applicant was rejected | 22.11.2016 | Date of oral proceedings | 28.11.2016 | Minutes of oral proceedings despatched | Divisional application(s) | The date of the Examining Division's first communication in respect of the earliest application for which a communication has been issued is 12.04.2010 | Fees paid | Renewal fee | 17.02.2010 | Renewal fee patent year 03 | 11.01.2011 | Renewal fee patent year 04 | 24.02.2012 | Renewal fee patent year 05 | 05.02.2013 | Renewal fee patent year 06 | 11.02.2014 | Renewal fee patent year 07 | 11.02.2015 | Renewal fee patent year 08 | 08.02.2016 | Renewal fee patent year 09 | Penalty fee | Additional fee for renewal fee | 31.03.2017 | 10 M06 Not yet paid |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [X] US2007001281 (ISHINO MASAKAZU et al.) | [Y] US2006270108 (FARNWORTH WARREN M et al.) | [A] AT7038 (DATACON SEMICONDUCTOR EQUIP et al.) [A] 1-20 * paragraphs [0065] - [0126]; figures 2-4 * | [A] US6534874 (MATSUMURA KAZUHIKO et al.) [A] 1-10 * the whole document * | [X] MATTHIAS T ET AL: "3D process integration. Wafer-to-wafer and chip-to-wafer bonding", ENABLING TECHNOLOGIES FOR 3-D INTEGRATION SYMPOSIUM - 27-29 NOVEMBER 2006,, 27 November 2006 (2006-11-27), pages 231 - 237, XP009104011 | [XY] CHRISTOPH SCHEIRING ET AL: "Advanced-Chip-to-Wafer Technology: Enabling Technology for Volume Production of 3D System Integration on Wafer Level", IMAPS 2004 : 37TH INTERNATIONAL SYMPOSIUM ON MICROELECTRONICS ; NOVEMBER 14 - 18, 2004, LONG BEACH CONVENTION CENTER, LONG BEACH, CALIFORNIA, USA,, 14 November 2004 (2004-11-14), pages 11p, XP009104027 [X] 1-6,9,10 * the whole document *[Y] 7,8 | Examination | US2008050904 | by applicant | US2007001281 |