-
EP2040288
European procedure
- EP About this file
- EP Legal status
- EP Federated register
- EP Event history
- EP Citations
- EP Patent family
- EP All documents
Extract from the Register of European Patents
EP About this file: EP2040288
| EP2040288 - Method of forming semiconductor chip wiring pattern using alignment marks [Right-click to bookmark this link] | Status | The application is deemed to be withdrawn Status updated on 24.08.2012 Database last updated on 08.10.2024 | Most recent event Tooltip | 24.08.2012 | Application deemed to be withdrawn | published on 26.09.2012 [2012/39] | Applicant(s) | For all designated states Shinko Electric Industries Co., Ltd. 80, Oshimada-machi Nagano-shi, Nagano 381-2287 / JP | [2009/13] | Inventor(s) | 01 /
Machida, Yoshihiro c/o Shinko Electric Industries Co., Ltd. 80, Oshimada-machi Nagano-shi Nagano 381-2287 / JP | [2009/13] | Representative(s) | Zimmermann & Partner Patentanwälte mbB Postfach 330 920 80069 München / DE | [N/P] |
| Former [2009/13] | Zimmermann & Partner Isartorplatz 1 80331 München / DE | Application number, filing date | 08164617.6 | 18.09.2008 | [2009/13] | Priority number, date | JP20070241374 | 18.09.2007 Original published format: JP 2007241374 | [2009/13] | Filing language | EN | Procedural language | EN | Publication | Type: | A2 Application without search report | No.: | EP2040288 | Date: | 25.03.2009 | Language: | EN | [2009/13] | Classification | IPC: | H01L21/60, H01L23/544 | [2009/13] | CPC: |
H01L23/544 (EP,US);
H01L21/78 (KR);
H01L23/3114 (EP,US);
H01L23/48 (KR);
H01L24/11 (EP,US);
H01L24/12 (EP,US);
H01L24/94 (EP,US);
H01L2223/5442 (EP,US);
H01L2223/5446 (EP,US);
H01L2224/0231 (EP,US);
H01L2224/02333 (EP,US);
H01L2224/0401 (EP,US);
H01L2224/05624 (EP,US);
H01L2224/06135 (EP);
H01L2224/13099 (EP,US);
H01L2224/274 (EP,US);
H01L2924/01005 (EP,US);
H01L2924/01006 (EP,US);
H01L2924/01013 (EP,US);
H01L2924/01022 (EP,US);
H01L2924/01023 (EP,US);
H01L2924/01029 (EP,US);
H01L2924/01033 (EP,US);
H01L2924/01074 (EP,US);
H01L2924/01078 (EP,US);
H01L2924/01079 (EP,US);
H01L2924/014 (EP,US);
H01L2924/14 (EP,US)
(-)
| C-Set: |
H01L2224/05624, H01L2924/00014 (EP,US)
| Designated contracting states | AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LI, LT, LU, LV, MC, MT, NL, NO, PL, PT, RO, SE, SI, SK, TR [2009/13] | Extension states | AL | Not yet paid | BA | Not yet paid | MK | Not yet paid | RS | Not yet paid | Title | German: | Herstellungsverfahren von Leiterbahnstrukturen eines Halbleiterbauelementes mittels Ausrichtungsmarkierungen | [2009/13] | English: | Method of forming semiconductor chip wiring pattern using alignment marks | [2009/13] | French: | Procédé de fabrication d'un circuit de connexion d'une puce à semi-conducteur en utilisant des marques d'alignement | [2009/13] | Examination procedure | 03.04.2012 | Application deemed to be withdrawn, date of legal effect [2012/39] | 10.05.2012 | Despatch of communication that the application is deemed to be withdrawn, reason: renewal fee not paid in time [2012/39] | Fees paid | Renewal fee | 29.09.2010 | Renewal fee patent year 03 | Penalty fee | Additional fee for renewal fee | 30.09.2011 | 04 M06 Not yet paid |
| Opt-out from the exclusive Tooltip competence of the Unified Patent Court | See the Register of the Unified Patent Court for opt-out data | ||
| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Cited in | by applicant | JP2002313985 |