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Extract from the Register of European Patents

EP About this file: EP2279520

EP2279520 - METHOD FOR MAKING COMPLEMENTARY P AND N MOSFET TRANSISTORS [Right-click to bookmark this link]
Former [2011/05]METHOD FOR MAKING COMPLEMENTARY P AND N MOSFET TRANSISTORS, ELECTRONIC DEVICE INCLUDING SUCH TRANSISTORS, AND PROCESSOR INCLUDING AT LEAST ONE SUCH DEVICE
[2018/19]
StatusNo opposition filed within time limit
Status updated on  02.08.2019
Database last updated on 11.09.2024
FormerThe patent has been granted
Status updated on  24.08.2018
FormerGrant of patent is intended
Status updated on  23.04.2018
Most recent event   Tooltip01.07.2022Lapse of the patent in a contracting state
New state(s): MK		published on 03.08.2022  [2022/31]
Applicant(s)For all designated states
Centre National de la Recherche Scientifique (C.N.R.S.)
3, rue Michel-Ange
75016 Paris / FR
[2018/39]
Former [2011/05]For all designated states
Centre National de la Recherche Scientifique - CNRS
3, rue Michel-Ange
75016 Paris / FR
Inventor(s)01 / LARRIEU, Guilhem
9 rue des Vétérans
F-59650 Villeneuve D'ascq / FR
02 / DUBOIS, Emmanuel
13 allée du Bel Air
F-59890 Quesnoy Sur Deule / FR
 [2011/05]
Representative(s)Lavoix
2, place d'Estienne d'Orves
75441 Paris Cedex 09 / FR
[2018/39]
Former [2011/05]Blot, Philippe Robert Emile
Cabinet Lavoix 2, place d'Estienne d'Orves
75441 Paris Cedex 09 / FR
Application number, filing date09742293.509.04.2009
[2011/05]
WO2009FR50642
Priority number, dateFR2008005246411.04.2008         Original published format: FR 0852464
[2011/05]
Filing languageFR
Procedural languageFR
PublicationType: A2 Application without search report
No.:WO2009136095
Date:12.11.2009
Language:FR
[2009/46]
Type: A2 Application without search report 
No.:EP2279520
Date:02.02.2011
Language:FR
The application published by WIPO in one of the EPO official languages on 12.11.2009 takes the place of the publication of the European patent application.
[2011/05]
Type: B1 Patent specification 
No.:EP2279520
Date:26.09.2018
Language:FR
[2018/39]
Search report(s)International search report - published on:EP30.12.2009
ClassificationIPC:H01L21/336, H01L29/78, H01L21/8238, H01L29/47, H01L21/265, H01L21/225, H01L29/66
[2018/19]
CPC:
H01L21/26513 (EP,US); H01L21/2257 (EP,US); H01L21/823814 (EP,US);
H01L21/84 (EP,US); H01L27/1203 (EP,US); H01L29/665 (EP,US);
H01L29/66643 (EP,US); H01L29/7839 (EP,US); H01L21/7624 (EP,US) (-)
Former IPC [2011/05]H01L21/336, H01L29/78, H01L21/8238, H01L29/47, H01L21/265, H01L21/225
Designated contracting statesAT,   BE,   BG,   CH,   CY,   CZ,   DE,   DK,   EE,   ES,   FI,   FR,   GB,   GR,   HR,   HU,   IE,   IS,   IT,   LI,   LT,   LU,   LV,   MC,   MK,   MT,   NL,   NO,   PL,   PT,   RO,   SE,   SI,   SK,   TR [2018/39]
Former [2011/05]AT,  BE,  BG,  CH,  CY,  CZ,  DE,  DK,  EE,  ES,  FI,  FR,  GB,  GR,  HR,  HU,  IE,  IS,  IT,  LI,  LT,  LU,  LV,  MC,  MK,  MT,  NL,  NO,  PL,  PT,  RO,  SE,  SI,  SK,  TR 
TitleGerman:VERFAHREN ZUR HERSTELLUNG KOMPLEMENTÄRER P- UND N-MOSFET-TRANSISTOREN[2018/19]
English:METHOD FOR MAKING COMPLEMENTARY P AND N MOSFET TRANSISTORS[2018/19]
French:PROCÉDÉ DE FABRICATION DE TRANSISTORS MOSFET COMPLÉMENTAIRES DE TYPE P ET N[2018/19]
Former [2011/05]VERFAHREN ZUR HERSTELLUNG KOMPLEMENTÄRER P- UND N-MOSFET-TRANSISTOREN, ELEKTRONISCHE VORRICHTUNG MIT DERARTIGEN TRANSISTOREN UND PROZESSOR MIT MINDESTENS EINER DERARTIGEN VORRICHTUNG
Former [2011/05]METHOD FOR MAKING COMPLEMENTARY P AND N MOSFET TRANSISTORS, ELECTRONIC DEVICE INCLUDING SUCH TRANSISTORS, AND PROCESSOR INCLUDING AT LEAST ONE SUCH DEVICE
Former [2011/05]PROCÉDÉ DE FABRICATION DE TRANSISTORS MOSFET COMPLÉMENTAIRES DE TYPE P ET N, ET DISPOSITIF ÉLECTRONIQUE COMPRENANT DE TELS TRANSISTORS, ET PROCESSEUR COMPRENANT AU MOINS UN TEL DISPOSITIF
Entry into regional phase04.11.2010National basic fee paid 
04.11.2010Designation fee(s) paid 
04.11.2010Examination fee paid 
Examination procedure04.11.2010Amendment by applicant (claims and/or description)
04.11.2010Examination requested  [2011/05]
17.07.2015Despatch of a communication from the examining division (Time limit: M04)
13.11.2015Reply to a communication from the examining division
24.04.2018Communication of intention to grant the patent
14.08.2018Fee for grant paid
14.08.2018Fee for publishing/printing paid
14.08.2018Receipt of the translation of the claim(s)
Divisional application(s)The date of the Examining Division's first communication in respect of the earliest application for which a communication has been issued is  17.07.2015
Opposition(s)27.06.2019No opposition filed within time limit [2019/36]
Fees paidRenewal fee
29.04.2011Renewal fee patent year 03
26.04.2012Renewal fee patent year 04
24.04.2013Renewal fee patent year 05
24.04.2014Renewal fee patent year 06
27.04.2015Renewal fee patent year 07
25.04.2016Renewal fee patent year 08
25.04.2017Renewal fee patent year 09
28.03.2018Renewal fee patent year 10
Opt-out from the exclusive  Tooltip
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Patent Court		 See the Register of the Unified Patent Court for opt-out data
Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court.
Lapses during opposition  TooltipHU09.04.2009
AT26.09.2018
CY26.09.2018
CZ26.09.2018
DK26.09.2018
EE26.09.2018
ES26.09.2018
FI26.09.2018
HR26.09.2018
LT26.09.2018
LV26.09.2018
MC26.09.2018
MK26.09.2018
MT26.09.2018
NL26.09.2018
PL26.09.2018
RO26.09.2018
SE26.09.2018
SI26.09.2018
SK26.09.2018
TR26.09.2018
BG26.12.2018
NO26.12.2018
GR27.12.2018
IS26.01.2019
PT26.01.2019
LU09.04.2019
BE30.04.2019
CH30.04.2019
LI30.04.2019
[2022/31]
Former [2021/34]HU09.04.2009
AT26.09.2018
CY26.09.2018
CZ26.09.2018
DK26.09.2018
EE26.09.2018
ES26.09.2018
FI26.09.2018
HR26.09.2018
LT26.09.2018
LV26.09.2018
MC26.09.2018
MT26.09.2018
NL26.09.2018
PL26.09.2018
RO26.09.2018
SE26.09.2018
SI26.09.2018
SK26.09.2018
TR26.09.2018
BG26.12.2018
NO26.12.2018
GR27.12.2018
IS26.01.2019
PT26.01.2019
LU09.04.2019
BE30.04.2019
CH30.04.2019
LI30.04.2019
Former [2021/32]HU09.04.2009
AT26.09.2018
CY26.09.2018
CZ26.09.2018
DK26.09.2018
EE26.09.2018
ES26.09.2018
FI26.09.2018
HR26.09.2018
LT26.09.2018
LV26.09.2018
MC26.09.2018
NL26.09.2018
PL26.09.2018
RO26.09.2018
SE26.09.2018
SI26.09.2018
SK26.09.2018
TR26.09.2018
BG26.12.2018
NO26.12.2018
GR27.12.2018
IS26.01.2019
PT26.01.2019
LU09.04.2019
BE30.04.2019
CH30.04.2019
LI30.04.2019
Former [2021/26]AT26.09.2018
CY26.09.2018
CZ26.09.2018
DK26.09.2018
EE26.09.2018
ES26.09.2018
FI26.09.2018
HR26.09.2018
LT26.09.2018
LV26.09.2018
MC26.09.2018
NL26.09.2018
PL26.09.2018
RO26.09.2018
SE26.09.2018
SI26.09.2018
SK26.09.2018
TR26.09.2018
BG26.12.2018
NO26.12.2018
GR27.12.2018
IS26.01.2019
PT26.01.2019
LU09.04.2019
BE30.04.2019
CH30.04.2019
LI30.04.2019
Former [2020/17]AT26.09.2018
CZ26.09.2018
DK26.09.2018
EE26.09.2018
ES26.09.2018
FI26.09.2018
HR26.09.2018
LT26.09.2018
LV26.09.2018
MC26.09.2018
NL26.09.2018
PL26.09.2018
RO26.09.2018
SE26.09.2018
SI26.09.2018
SK26.09.2018
TR26.09.2018
BG26.12.2018
NO26.12.2018
GR27.12.2018
IS26.01.2019
PT26.01.2019
LU09.04.2019
BE30.04.2019
CH30.04.2019
LI30.04.2019
Former [2020/11]AT26.09.2018
CZ26.09.2018
DK26.09.2018
EE26.09.2018
ES26.09.2018
FI26.09.2018
HR26.09.2018
LT26.09.2018
LV26.09.2018
MC26.09.2018
NL26.09.2018
PL26.09.2018
RO26.09.2018
SE26.09.2018
SI26.09.2018
SK26.09.2018
BG26.12.2018
NO26.12.2018
GR27.12.2018
IS26.01.2019
PT26.01.2019
LU09.04.2019
BE30.04.2019
CH30.04.2019
LI30.04.2019
Former [2020/04]AT26.09.2018
CZ26.09.2018
DK26.09.2018
EE26.09.2018
ES26.09.2018
FI26.09.2018
HR26.09.2018
LT26.09.2018
LV26.09.2018
MC26.09.2018
NL26.09.2018
PL26.09.2018
RO26.09.2018
SE26.09.2018
SI26.09.2018
SK26.09.2018
BG26.12.2018
NO26.12.2018
GR27.12.2018
IS26.01.2019
PT26.01.2019
LU09.04.2019
Former [2020/02]AT26.09.2018
CZ26.09.2018
DK26.09.2018
EE26.09.2018
ES26.09.2018
FI26.09.2018
HR26.09.2018
LT26.09.2018
LV26.09.2018
MC26.09.2018
NL26.09.2018
PL26.09.2018
RO26.09.2018
SE26.09.2018
SI26.09.2018
SK26.09.2018
BG26.12.2018
NO26.12.2018
GR27.12.2018
IS26.01.2019
PT26.01.2019
Former [2019/50]AT26.09.2018
CZ26.09.2018
DK26.09.2018
EE26.09.2018
ES26.09.2018
FI26.09.2018
HR26.09.2018
LT26.09.2018
LV26.09.2018
NL26.09.2018
PL26.09.2018
RO26.09.2018
SE26.09.2018
SI26.09.2018
SK26.09.2018
BG26.12.2018
NO26.12.2018
GR27.12.2018
IS26.01.2019
PT26.01.2019
Former [2019/34]AT26.09.2018
CZ26.09.2018
DK26.09.2018
EE26.09.2018
ES26.09.2018
FI26.09.2018
HR26.09.2018
LT26.09.2018
LV26.09.2018
NL26.09.2018
PL26.09.2018
RO26.09.2018
SE26.09.2018
SK26.09.2018
BG26.12.2018
NO26.12.2018
GR27.12.2018
IS26.01.2019
PT26.01.2019
Former [2019/26]AT26.09.2018
CZ26.09.2018
EE26.09.2018
ES26.09.2018
FI26.09.2018
HR26.09.2018
LT26.09.2018
LV26.09.2018
NL26.09.2018
PL26.09.2018
RO26.09.2018
SE26.09.2018
SK26.09.2018
BG26.12.2018
NO26.12.2018
GR27.12.2018
IS26.01.2019
PT26.01.2019
Former [2019/23]AT26.09.2018
CZ26.09.2018
EE26.09.2018
ES26.09.2018
FI26.09.2018
HR26.09.2018
LT26.09.2018
LV26.09.2018
NL26.09.2018
PL26.09.2018
RO26.09.2018
SE26.09.2018
SK26.09.2018
BG26.12.2018
NO26.12.2018
GR27.12.2018
IS26.01.2019
Former [2019/22]CZ26.09.2018
FI26.09.2018
HR26.09.2018
LT26.09.2018
LV26.09.2018
NL26.09.2018
PL26.09.2018
RO26.09.2018
SE26.09.2018
BG26.12.2018
NO26.12.2018
GR27.12.2018
IS26.01.2019
Former [2019/21]FI26.09.2018
HR26.09.2018
LT26.09.2018
LV26.09.2018
NL26.09.2018
SE26.09.2018
BG26.12.2018
NO26.12.2018
GR27.12.2018
IS26.01.2019
Former [2019/20]FI26.09.2018
HR26.09.2018
LT26.09.2018
LV26.09.2018
NL26.09.2018
SE26.09.2018
BG26.12.2018
NO26.12.2018
GR27.12.2018
Former [2019/12]FI26.09.2018
HR26.09.2018
LT26.09.2018
LV26.09.2018
SE26.09.2018
BG26.12.2018
NO26.12.2018
GR27.12.2018
Former [2019/11]FI26.09.2018
HR26.09.2018
LT26.09.2018
SE26.09.2018
BG26.12.2018
NO26.12.2018
GR27.12.2018
Former [2019/10]FI26.09.2018
LT26.09.2018
SE26.09.2018
BG26.12.2018
NO26.12.2018
GR27.12.2018
Former [2019/08]FI26.09.2018
LT26.09.2018
NO26.12.2018
Former [2019/07]LT26.09.2018
Cited inInternational search[A]GB2124428  (WESTERN ELECTRIC CO) [A] 1-13* figure -; claims 1-25 *;
 [X]EP1763084  (FUJITSU LTD [JP]) [X] 1-13 * paragraphs [0032] , [0033]; figures 1-36 *;
 [X]  - BERA L K ET AL, "Dopant-Segregated Ni-Silicide Schottky-Source/Drain CMOS on Strained-Si/SiGe Multiple Quantum-Well Channel on Bulk-Si", SOLID-STATE DEVICE RESEARCH CONFERENCE, 2006. ESSDERC 2006. PROCEEDING OF THE 36TH EUROPEAN, IEEE, PI, (20060901), ISBN 978-1-4244-0301-1, pages 290 - 293, XP031047050 [X] 1,3,4,6,7,9,11 * page 290 - page 291; figure 9; table 1 *

DOI:   http://dx.doi.org/10.1109/ESSDER.2006.307695
 [X]  - QIU Z J ET AL, "Role of Si implantation in control of underlap length in Schottky-barrier source/drain MOSFETs on ultrathin body SOI", ULTIMATE INTEGRATION OF SILICON, 2008. ULIS 2008. 9TH INTERNATIONAL CONFERENCE ON, IEEE, PISCATAWAY, NJ, USA, (20080312), ISBN 978-1-4244-1729-2, pages 175 - 178, XP031256604 [X] 1,2,4,6,7,9,11 * page 175 - page 177; figure - *
 [X]  - ZHIJUN QIU ET AL, "A Comparative Study of Two Different Schemes to Dopant Segregation at NiSi/Si and PtSi/Si Interfaces for Schottky Barrier Height Lowering", IEEE TRANSACTIONS ON ELECTRON DEVICES, IEEE SERVICE CENTER, PISACATAWAY, NJ, US, (20080101), vol. 54, no. 1, ISSN 0018-9383, pages 396 - 403, XP011199367 [X] 1-4,6,7,9-11 * page 396 - page 402; figure 1; table 1 *
 [A]  - KINOSHITA A ET AL, "High-performance 50-nm-gate-length schottky-source/drain MOSFETs with dopant-segregation junctions", VLSI TECHNOLOGY, 2005. DIGEST OF TECHNICAL PAPERS. 2005 SYMPOSIUM ON KYOTO, JAPAN JUNE 14-16, 2005, PISCATAWAY, NJ, USA,IEEE, (20050614), ISBN 978-4-900784-00-0, pages 158 - 159, XP010818281 [A] 1-13 * page 152; figure 1 *

DOI:   http://dx.doi.org/10.1109/.2005.1469250
    [ ] - KINOSHITA A ET AL, "Solution for high-performance Schottky-source/drain MOSFETs: Schottky barrier height engineering with dopant segregation technique", VLSI TECHNOLOGY, 2004. DIGEST OF TECHNICAL PAPERS. 2004 SYMPOSIUM ON HONOLULU, HI, USA JUNE 15-17, 2004, PISCATAWAY, NJ, USA,IEEE, (20040615), ISBN 978-0-7803-8289-3, pages 168 - 169, XP010732846

DOI:   http://dx.doi.org/10.1109/VLSIT.2004.1345459
 [A]  - MATSUMOTO S ET AL, "CMOS APPLICATION OF SCHOTTKY SOURCE/DRAIN SOI MOSFET WITH SHALLOW DOPED EXTENSION", JAPANESE JOURNAL OF APPLIED PHYSICS, JAPAN SOCIETY OF APPLIED PHYSICS, TOKYO.; JP, (20040401), vol. 43, no. 4B, ISSN 0021-4922, pages 2170 - 2175, XP001227735 [A] 1-13 * page 2170 - page 2174; figure - *

DOI:   http://dx.doi.org/10.1143/JJAP.43.2170
Examination   - "8.3.1 Aufbau der MOS-Transistoren und ihrer Isolation", D Widmann, H Mader, H Friedrich, Technologie hochintegrierter Schaltungen, 2. Auflage, Springer Verlag Berlin Heidelberg New York, (19960101), pages 275 - 283, ISBN 3-540-59357-8
    - WIDMANN D ET AL, TECHNOLOGIE HOCHINTEGRIERTER SCHALTUNGEN, DETAILLIERTE PROZESSFOLGE AUSGEWÀHLTER GESAMTPROZESSE, TECHNOLOGIE HOCHINTEGRIERTER SCHALTUNGEN, SPRINGER VERLAG, DE, PAGE(S) 309 - 318, (19960101), ISBN 978-3-540-59357-7, XP007914877
The EPO accepts no responsibility for the accuracy of data originating from other authorities; in particular, it does not guarantee that it is complete, up to date or fit for specific purposes.