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EP2378548
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EP About this file: EP2378548
| EP2378548 - Method of processing and inspecting semiconductor substrates [Right-click to bookmark this link] | |||
| Former [2011/42] | Methods of processing and inspecting semiconductor substrates | ||
| [2015/14] | Status | The application is deemed to be withdrawn Status updated on 19.02.2016 Database last updated on 24.04.2024 | Most recent event Tooltip | 19.02.2016 | Application deemed to be withdrawn | published on 23.03.2016 [2016/12] | Applicant(s) | For all designated states Nanda Technologies GmbH Lise-Meitner-Strasse 3 85716 Unterschleissheim / DE | For all designated states IMEC Kapeldreef 75 3001 Leuven / BE | [2011/42] | Inventor(s) | 01 /
Markwort, Lars Dachauer Strasse 59D 85778 Haimhausen / DE | 02 /
Guittet, Pierre-Yves Tizianstrasse 112 80638 München / DE | 03 /
Halder, Sandip c/o Imec Kapeldreef 75 3001 Leuven / BE | 04 /
Jourdain, Anne c/o Imec Kapeldreef 75 3001 Leuven / BE | [2011/42] | Representative(s) | Diehl & Partner Patent- und Rechtsanwaltskanzlei mbB Erika-Mann-Straße 9 80636 München / DE | [N/P] |
| Former [2011/42] | Diehl & Partner GbR Patentanwälte Augustenstrasse 46 80333 München / DE | Application number, filing date | 10004141.7 | 19.04.2010 | [2011/42] | Filing language | EN | Procedural language | EN | Publication | Type: | A1 Application with search report | No.: | EP2378548 | Date: | 19.10.2011 | Language: | EN | [2011/42] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 01.09.2010 | Classification | IPC: | G01N21/95, H01L21/768, H01L21/66 | [2015/14] | CPC: |
H01L22/12 (EP,US);
G01N21/9501 (EP,US);
H01L21/76898 (EP,US);
H01L22/26 (EP,US);
G01N21/9505 (EP,US)
|
| Former IPC [2011/42] | H01L21/66 | Designated contracting states | AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LI, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, SE, SI, SK, SM, TR [2011/42] | Extension states | AL | Not yet paid | BA | Not yet paid | ME | Not yet paid | RS | Not yet paid | Title | German: | Verfahren zur Prozessierung und Untersuchung von Halbleitersubstraten | [2011/42] | English: | Method of processing and inspecting semiconductor substrates | [2015/14] | French: | Procédé de traitement et d'inspection de substrats semi-conducteurs | [2015/14] |
| Former [2011/42] | Methods of processing and inspecting semiconductor substrates | ||
| Former [2011/42] | Procédés de traitement et d'inspection de substrats de semi-conducteur | Examination procedure | 29.03.2011 | Examination requested [2011/42] | 06.05.2011 | Despatch of a communication from the examining division (Time limit: M04) | 06.09.2011 | Reply to a communication from the examining division | 31.05.2012 | Despatch of a communication from the examining division (Time limit: M06) | 10.12.2012 | Reply to a communication from the examining division | 11.02.2013 | Despatch of a communication from the examining division (Time limit: M06) | 19.08.2013 | Reply to a communication from the examining division | 09.10.2013 | Despatch of a communication from the examining division (Time limit: M06) | 22.04.2014 | Reply to a communication from the examining division | 18.06.2014 | Despatch of a communication from the examining division (Time limit: M06) | 26.11.2014 | Reply to a communication from the examining division | 18.05.2015 | Communication of intention to grant the patent | 29.09.2015 | Application deemed to be withdrawn, date of legal effect [2016/12] | 04.11.2015 | Despatch of communication that the application is deemed to be withdrawn, reason: fee for grant / fee for printing not paid in time [2016/12] | Divisional application(s) | The date of the Examining Division's first communication in respect of the earliest application for which a communication has been issued is 06.05.2011 | Fees paid | Renewal fee | 29.03.2012 | Renewal fee patent year 03 | 12.04.2013 | Renewal fee patent year 04 | 25.03.2014 | Renewal fee patent year 05 | 10.04.2015 | Renewal fee patent year 06 |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [A]US4933567 (SILVA ROBERT M [US], et al) [A] 2,3,7-10,13 * column 6, line 17 - line 24 * * column 6, line 36 - line 52 ** column 10, line 17 - column 11, line 2 *; | [XYI]US2009008794 (WU WENG-JIN [TW], et al) [X] 1,6-13,15 * paragraph [0035] - paragraph [0049]; figures 2-4,8,10 * * paragraph [0053] * [Y] 2-5 [I] 14; | [XI]US2009227047 (YANG KU-FENG [TW], et al) [X] 1,8,10-12,15 * paragraphs [0032] , [0067] , [0072]; figures 1-4, 8 * [I] 3,6,14; | [YD]WO2009121628 (NANDA TECHNOLOGIES GMBH [DE], et al) [YD] 2-5 * page 20, line 3 - line 6; figure 3 * | Examination | - ABT I ET AL, "Characterization of silicon microstrip detectors using an infrared laser system", NUCLEAR INSTRUMENTS & METHODS IN PHYSICS RESEARCH. SECTION A: ACCELERATORS, SPECTROMETERS, DETECTORS, AND ASSOCIATED EQUIPMENT, ELSEVIER BV * NORTH-HOLLAND, NETHERLANDS, (19990301), vol. 423, no. 2-3, doi:10.1016/S0168-9002(98)01337-0, ISSN 0168-9002, pages 303 - 319, XP004160862 DOI: http://dx.doi.org/10.1016/S0168-9002(98)01337-0 | by applicant | US6916725 | US2005158889 | US7214615 | WO2009121628 | US2010032764 | US2010038800 | US2010041226 | - ANNE JOURDAIN ET AL., "New Hybrid Bonding Approach for 3D Stacking of ICs", CHIP SCALE REVIEW, (200908), pages 24 - 28 |