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Extract from the Register of European Patents

EP About this file: EP2267769

EP2267769 - DRAM transistor with a gate formed in a substrate trench [Right-click to bookmark this link]
StatusThe application has been withdrawn
Status updated on  19.02.2016
Database last updated on 30.09.2024
Most recent event   Tooltip19.02.2016Withdrawal of applicationpublished on 23.03.2016  [2016/12]
Applicant(s)For all designated states
Micron Technology, Inc.
8000 South Federal Way
Boise, ID 83716 / US
[2010/52]
Inventor(s)01 / Sanh, Tang
1273 N. Jullion Avenue
Boise, ID 83704 / US
02 / Haller, Gordon
5426 East Quartersawn
Boise, ID 83716 / US
03 / Brown, Kris
8610 W. Atwater
Garden City, ID 83714 / US
04 / Earl, Allen, T., III
2200 W. King Road
Kuna, ID 83634 / US
 [2010/52]
Representative(s)Beresford, Keith Denis Lewis
Beresford Crump LLP
16 High Holborn
London WC1V 6BX / GB
[N/P]
Former [2010/52]Beresford, Keith Denis Lewis
Beresford & Co. 16 High Holborn London
WC1V 6BX / GB
Application number, filing date10011474.329.08.2005
[2010/52]
Priority number, dateUS2004093215001.09.2004         Original published format: US 932150
[2010/52]
Filing languageEN
Procedural languageEN
PublicationType: A2 Application without search report 
No.:EP2267769
Date:29.12.2010
Language:EN
[2010/52]
Type: A3 Search report 
No.:EP2267769
Date:24.08.2011
[2011/34]
Search report(s)(Supplementary) European search report - dispatched on:EP27.07.2011
ClassificationIPC:H01L21/8242, H01L27/108, H01L21/336, H01L29/10, H01L29/417, // H01L29/78, H01L29/423
[2011/34]
CPC:
H01L29/41758 (EP,US); H10B99/00 (KR); H01L21/18 (KR);
H01L29/1037 (EP,US); H01L29/4238 (EP,US); H01L29/66621 (EP,US);
H10B12/00 (KR); H10B12/053 (EP,US); H10B12/34 (EP,US);
H01L29/4236 (EP,US); H01L29/78 (EP,US); H10B12/318 (EP,US);
H10B12/482 (EP,US) (-)
Former IPC [2010/52]H01L21/8242, H01L27/108, H01L21/336, H01L29/78, H01L29/423
Designated contracting statesAT,   BE,   BG,   CH,   CY,   CZ,   DE,   DK,   EE,   ES,   FI,   FR,   GB,   GR,   HU,   IE,   IS,   IT,   LI,   LT,   LU,   LV,   MC,   NL,   PL,   PT,   RO,   SE,   SI,   SK,   TR [2010/52]
Extension statesALNot yet paid
BANot yet paid
HRNot yet paid
MKNot yet paid
YUNot yet paid
TitleGerman:DRAM-Transistor mit einem in einem Substratgraben ausgebildeten Gatter[2010/52]
English:DRAM transistor with a gate formed in a substrate trench[2010/52]
French:Transistor pour une mémoire du type DRAM ayant une grille formée dans une tranchée dans le substrat[2010/52]
Examination procedure23.02.2012Amendment by applicant (claims and/or description)
23.02.2012Examination requested  [2012/15]
07.05.2012Despatch of a communication from the examining division (Time limit: M06)
19.11.2012Reply to a communication from the examining division
10.04.2014Despatch of a communication from the examining division (Time limit: M04)
12.08.2014Reply to a communication from the examining division
18.02.2016Application withdrawn by applicant  [2016/12]
Parent application(s)   TooltipEP05792363.3  / EP1784858
Divisional application(s)The date of the Examining Division's first communication in respect of the earliest application for which a communication has been issued (EP20050792363) is  05.06.2007
Fees paidRenewal fee
27.10.2010Renewal fee patent year 03
27.10.2010Renewal fee patent year 04
27.10.2010Renewal fee patent year 05
27.10.2010Renewal fee patent year 06
11.08.2011Renewal fee patent year 07
10.08.2012Renewal fee patent year 08
19.08.2013Renewal fee patent year 09
13.08.2014Renewal fee patent year 10
10.08.2015Renewal fee patent year 11
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Documents cited:Search[A]US5244824  (SIVAN RICHARD D [US]);
 [XAI]US5480838  (MITSUI KATSUYOSHI [JP]);
 [A]DE19928781  (SIEMENS AG [DE]);
 [IA]US2003170941  (COLAVITO DAVID B [US], et al)
by applicantUS2003234414
The EPO accepts no responsibility for the accuracy of data originating from other authorities; in particular, it does not guarantee that it is complete, up to date or fit for specific purposes.