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EP2360601
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EP About this file: EP2360601
| EP2360601 - Programmable logic device with custom blocks [Right-click to bookmark this link] | Status | The application is deemed to be withdrawn Status updated on 20.07.2012 Database last updated on 03.10.2024 | Most recent event Tooltip | 20.07.2012 | Application deemed to be withdrawn | published on 22.08.2012 [2012/34] | Applicant(s) | For all designated states Panasonic Corporation 1006, Oaza Kadoma Kadoma-shi Osaka 571-8501 / JP | [N/P] |
| Former [2011/34] | For all designated states Panasonic Corporation 1006, Oaza Kadoma Kadoma-shi Osaka 571-8501 / JP | Inventor(s) | 01 /
Olgiati, Andrea c/o Panasonic Strategic Semiconductor Development Centre Europe 1, Friary Temple Quay Bristol, Bristol BS1 6EA / GB | 02 /
Stansfield, Tony c/o Panasonic Strategic Semiconductor Development Centre Europe 1 Friary Temple Quay Bristol, Bristol BS1 6EA / GB | 03 /
Deeley, Simon c/o Panasonic Strategic Semiconductor Development Centre Europe 1 Friary Temple Quay Bristol, Bristol BS1 6EA / GB | [2011/34] | Representative(s) | Haley, Stephen Gill Jennings & Every LLP The Broadgate Tower 20 Primrose Street London EC2A 2ES / GB | [N/P] |
| Former [2011/34] | Haley, Stephen Gill Jennings & Every LLP The Broadgate Tower 20 Primrose Street London EC2A 2ES / GB | Application number, filing date | 10153725.6 | 16.02.2010 | [2011/34] | Filing language | EN | Procedural language | EN | Publication | Type: | A1 Application with search report | No.: | EP2360601 | Date: | 24.08.2011 | Language: | EN | [2011/34] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 07.10.2010 | Classification | IPC: | G06F15/78, H03K19/177 | [2011/34] | CPC: |
G06F15/7867 (EP,US);
H03K19/17736 (EP,US);
H03K19/17796 (EP,US)
| Designated contracting states | AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LI, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, SE, SI, SK, SM, TR [2011/34] | Extension states | AL | Not yet paid | BA | Not yet paid | RS | Not yet paid | Title | German: | Programmierbare logische Vorrichtung mit maßgeschneiderten Blöcken | [2011/34] | English: | Programmable logic device with custom blocks | [2011/34] | French: | Dispositif logique programmable avec blocs personnalisés | [2011/34] | Examination procedure | 25.02.2012 | Application deemed to be withdrawn, date of legal effect [2012/34] | 03.04.2012 | Despatch of communication that the application is deemed to be withdrawn, reason: examination fee not paid in time [2012/34] | Fees paid | Penalty fee | Additional fee for renewal fee | 29.02.2012 | 03 M06 Not yet paid |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [XI]US2003062922 (DOUGLASS STEPHEN M [US], et al) [X] 1,2 * figure 2 * * figure 9 * * figure 10B * * figure 11 * * paragraphs [0004] , [0026] , [0030] , [0036] * * paragraphs [0039] - [0041] * * paragraph [0053] * [I] 3-8; | [A]US7635987 (AGARWAL ANANT [US]) [A] 1-8 * the whole document * | [XI] - "Virtex-II Pro Platform FPGAs: Functional Description DS083-2 (v2.5)", PRODUCT SPECIFICATION XILINX, XX, XX, (20030120), pages 13 - 46, XP002279387 [X] 1-6 * figure 9 * * figure 22 * * figure 31 * * figure 36 * * figure 43 * * figure 54 * * figure 35 * * page 36, column right, line 25 - line 31 * * page 41, column left, line 45 - column right, line 28 * [I] 7,8 | by applicant | US6353841 | US6252792 | US2002157066 |