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Extract from the Register of European Patents

EP About this file: EP2261993

EP2261993 - Semiconductor device [Right-click to bookmark this link]
Former [2010/50]Semiconductor device and method for making the same
[2014/33]
StatusNo opposition filed within time limit
Status updated on  06.11.2015
Database last updated on 29.07.2024
Most recent event   Tooltip06.11.2015No opposition filed within time limitpublished on 09.12.2015  [2015/50]
Applicant(s)For all designated states
Fujitsu Semiconductor Limited
2-10-23 Shin-Yokohama Kohoku-ku, Yokohama-shi
Kanagawa 222-0033 / JP
[2010/50]
Inventor(s)01 / Honda, Toshiyuki
c/o FUJITSU LIMITED
1-1, Kamikodanaka 4-chome
Nakahara-ku
Kawasaki-shi Kanagawa 211-8588 / JP
02 / Tsuji, Kazuto
c/o FUJITSU LIMITED
1-1, Kamikodanaka 4-chome
Nakahara-ku
Kawasaki-shi Kanagawa 211-8588 / JP
03 / Onodera, Masanori
c/o FUJITSU LIMITED
1-1, Kamikodanaka 4-chome
Nakahara-ku
Kawasaki-shi Kanagawa 211-8588 / JP
04 / Aoki, Hiroshi
c/o FUJITSU LIMITED
1-1, Kamikodanaka 4-chome
Nakahara-ku
Kawasaki-shi Kanagawa 211-8588 / JP
05 / Kobayashi, Izumi
c/o FUJITSU LIMITED
1-1, Kamikodanaka 4-chome
Nakahara-ku
Kawasaki-shi Kanagawa 211-8588 / JP
06 / Moriya, Susumu
c/o FUJITSU LIMITED
1-1, Kamikodanaka 4-chome
Nakahara-ku
Kawasaki-shi Kanagawa 211-8588 / JP
07 / Kaiya, Hiroshi
c/o FUJITSU LIMITED
1-1, Kamikodanaka 4-chome
Nakahara-ku
Kawasaki-shi Kanagawa 211-8588 / JP
 [2015/01]
Former [2010/50]01 / Honda, Toshiyuki
c/o FUJITSU LIMITED 1-1, Kamikodanaka 4-chome Nakahara-ku
Kawasaki-shi Kanagawa 211-8588 / JP
02 / Tsuji, Kazuto
c/o FUJITSU LIMITED 1-1, Kamikodanaka 4-chome Nakahara-ku
Kawasaki-shi Kanagawa 211-8588 / JP
03 / Onodera, Masanori
c/o FUJITSU LIMITED 1-1, Kamikodanaka 4-chome Nakahara-ku
Kawasaki-shi Kanagawa 211-8588 / JP
04 / Aoki, Hiroshi
c/o FUJITSU LIMITED 1-1, Kamikodanaka 4-chome Nakahara-ku
Kawasaki-shi Kanagawa 211-8588 / JP
05 / Kobayashi, Izumi
c/o FUJITSU LIMITED 1-1, Kamikodanaka 4-chome Nakahara-ku
Kawasaki-shi Kanagawa 211-8588 / JP
06 / Moriya, Susumu
c/o FUJITSU LIMITED 1-1, Kamikodanaka 4-chome Nakahara-ku
Kawasaki-shi Kanagawa 211-8588 / JP
07 / Kaiya, Hiroshi
c/o FUJITSU LIMITED 1-1, Kamikodanaka 4-chome Nakahara-ku
Kawasaki-shi Kanagawa 211-8588 / JP
Representative(s)Stebbing, Timothy Charles
Haseltine Lake LLP
Lincoln House, 5th Floor
300 High Holborn
London WC1V 7JH / GB
[2015/01]
Former [2010/50]Stebbing, Timothy Charles
Haseltine Lake LLP 5th Floor, Lincoln House 300 High Holborn
London, Greater London WC1V 7JH / GB
Application number, filing date10181125.510.12.2001
[2010/50]
Priority number, dateJP2001005573528.02.2001         Original published format: JP 2001055735
JP2001031567212.10.2001         Original published format: JP 2001315672
[2010/50]
Filing languageEN
Procedural languageEN
PublicationType: A2 Application without search report 
No.:EP2261993
Date:15.12.2010
Language:EN
[2010/50]
Type: A3 Search report 
No.:EP2261993
Date:11.07.2012
Language:EN
[2012/28]
Type: B1 Patent specification 
No.:EP2261993
Date:31.12.2014
Language:EN
[2015/01]
Search report(s)(Supplementary) European search report - dispatched on:EP12.06.2012
ClassificationIPC:H01L31/02, H05K1/02, H04N5/225, H01L27/146, H01L31/0203, H01L31/0232, H04N7/14
[2014/33]
CPC:
H01L31/0203 (EP,US); H01L27/14 (KR); H01L27/14618 (EP,US);
H01L27/14625 (EP,US); H01L27/14683 (EP,US); H01L31/02002 (EP,US);
H01L31/02325 (EP,US); H04N23/54 (EP,US); H04N23/55 (EP,US);
H01L2224/48227 (EP,US); H01L2924/01322 (EP,US); H04N2007/145 (EP,US);
H05K1/0284 (EP,US); H05K3/205 (EP,US); H05K3/4007 (EP,US) (-)
C-Set:
H01L2224/48091, H01L2924/00014 (EP,US);
H01L2924/01322, H01L2924/00 (US,EP)
Former IPC [2012/13]H01L27/146, H01L31/0203, H01L31/0232
Former IPC [2010/50]H01L31/02, H01L31/0203, H01L31/0232
Designated contracting statesDE,   FR,   GB [2010/50]
TitleGerman:Halbleitervorrichtung[2014/33]
English:Semiconductor device[2014/33]
French:Dispositif à semi-conducteur[2014/33]
Former [2010/50]Halbleitervorrichtung und dessen Verfahren zur Herstellung
Former [2010/50]Semiconductor device and method for making the same
Former [2010/50]Dispositif à semi-conducteur et son procédé de fabrication
Examination procedure04.01.2013Amendment by applicant (claims and/or description)
07.01.2013Examination requested  [2013/08]
19.03.2013Despatch of a communication from the examining division (Time limit: M04)
29.07.2013Reply to a communication from the examining division
23.08.2013Despatch of a communication from the examining division (Time limit: M05)
15.01.2014Reply to a communication from the examining division
06.08.2014Communication of intention to grant the patent
18.11.2014Receipt of the translation of the claim(s)
19.11.2014Fee for grant paid
19.11.2014Fee for publishing/printing paid
Parent application(s)   TooltipEP01310313.0  / EP1237202
Divisional application(s)The date of the Examining Division's first communication in respect of the earliest application for which a communication has been issued (EP20010310313) is  31.05.2007
Opposition(s)01.10.2015No opposition filed within time limit [2015/50]
Fees paidRenewal fee
22.12.2010Renewal fee patent year 03
22.12.2010Renewal fee patent year 04
22.12.2010Renewal fee patent year 05
22.12.2010Renewal fee patent year 06
22.12.2010Renewal fee patent year 07
22.12.2010Renewal fee patent year 08
22.12.2010Renewal fee patent year 09
22.12.2010Renewal fee patent year 10
23.12.2011Renewal fee patent year 11
02.10.2012Renewal fee patent year 12
02.10.2013Renewal fee patent year 13
03.10.2014Renewal fee patent year 14
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Documents cited:Search[X]JP2000049319  ;
 [A]JP2001008068  ;
 [A]JPH11191865  ;
 [A]JPH0799214  (TOSHIBA CORP, et al)
The EPO accepts no responsibility for the accuracy of data originating from other authorities; in particular, it does not guarantee that it is complete, up to date or fit for specific purposes.