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EP2378549
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EP About this file: EP2378549
| EP2378549 - Method for manufacturing a semiconductor substrate [Right-click to bookmark this link] | Status | The application is deemed to be withdrawn Status updated on 20.02.2015 Database last updated on 07.10.2024 | Most recent event Tooltip | 20.02.2015 | Application deemed to be withdrawn | published on 25.03.2015 [2015/13] | Applicant(s) | For all designated states Soitec Parc Technologique des Fontaines Chemin des Franques 38190 Bernin / FR | [2012/19] |
| Former [2011/42] | For all designated states S.O.I.Tec Silicon on Insulator Technologies Parc Technologique des Fontaines Chemin des Franques 38190 Bernin / FR | Inventor(s) | 01 /
Mazure, Carlos 143 Chemin du Bas Bernin Residence Cidex 64a 38190 Bernin / FR | 02 /
Bourdelle, Konstantin 22 rue du Luisset 38920 Crolles / FR | 03 /
Ferrant, Richard Village de Suguensou 29770 Esquibien / DE | 04 /
Nguyen, Bich-Yen 110 S. Laurelwood Drive Austin, TX 78733 / US | [2011/42] | Representative(s) | Grünecker Patent- und Rechtsanwälte PartG mbB Leopoldstraße 4 80802 München / DE | [N/P] |
| Former [2011/42] | Grünecker, Kinkeldey, Stockmair & Schwanhäusser Leopoldstrasse 4 80802 München / DE | Application number, filing date | 11001643.3 | 06.04.2010 | [2011/42] | Filing language | EN | Procedural language | EN | Publication | Type: | A1 Application with search report | No.: | EP2378549 | Date: | 19.10.2011 | Language: | EN | [2011/42] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 02.05.2011 | Classification | IPC: | H01L21/762, H01L21/18, H01L21/20 | [2014/18] | CPC: |
H01L21/76254 (EP,US);
H01L27/12 (KR);
H01L21/187 (EP,US);
H01L21/20 (KR);
H01L21/2007 (EP,US);
H01L21/76251 (EP,US)
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| Former IPC [2011/42] | H01L21/762 | Designated contracting states | AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LI, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, SE, SI, SK, SM, TR [2011/42] | Extension states | AL | Not yet paid | BA | Not yet paid | ME | Not yet paid | RS | Not yet paid | Title | German: | Verfahren zur Herstellung eines Halbleitersubstrats | [2011/42] | English: | Method for manufacturing a semiconductor substrate | [2011/42] | French: | Procédé de fabrication d'un substrat semi-conducteur | [2011/42] | Examination procedure | 04.01.2012 | Amendment by applicant (claims and/or description) | 04.01.2012 | Examination requested [2012/08] | 08.02.2012 | Despatch of a communication from the examining division (Time limit: M04) | 15.06.2012 | Reply to a communication from the examining division | 06.03.2013 | Despatch of a communication from the examining division (Time limit: M04) | 25.06.2013 | Reply to a communication from the examining division | 19.05.2014 | Communication of intention to grant the patent | 30.09.2014 | Application deemed to be withdrawn, date of legal effect [2015/13] | 06.11.2014 | Despatch of communication that the application is deemed to be withdrawn, reason: fee for grant / fee for printing not paid in time [2015/13] | Parent application(s) Tooltip | EP10290181.6 / EP2375442 | Divisional application(s) | The date of the Examining Division's first communication in respect of the earliest application for which a communication has been issued (EP20100290181) is 08.02.2012 | Fees paid | Renewal fee | 26.03.2012 | Renewal fee patent year 03 | 24.04.2013 | Renewal fee patent year 04 | 24.04.2014 | Renewal fee patent year 05 |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [XI]FR2925223 (SOITEC SILICON ON INSULATOR [FR]) [X] 1,6-10 * page 3, line 18 - page 27, line 16; figures 3,7 * [I] 4,5; | [X]EP1081748 (LUCENT TECHNOLOGIES INC [US]) [X] 1,8-10 * column 2, paragraph 8 - column 5, paragraph 20; figures 1-6 *; | [X]US2005255666 (YANG XIAO C [US]) [X] 1,8 * page 2, paragraph 12 - page 3, paragraph 32; figures 1-3 * |