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Extract from the Register of European Patents

EP About this file: EP2564996

EP2564996 - A method of generating a hole or recess or well in an electrically insulating or semiconducting substrate [Right-click to bookmark this link]
StatusThe application is deemed to be withdrawn
Status updated on  02.12.2016
Database last updated on 14.09.2024
Most recent event   Tooltip02.12.2016Application deemed to be withdrawnpublished on 04.01.2017  [2017/01]
Applicant(s)For all designated states
Asahi Glass Company, Limited
Shin-Marunouchi Building
1-5-1 Marunouchi
Chiyoda-ku
Tokyo 100-8405 / JP
[2013/10]
Inventor(s)01 / Schmidt, Christian
Zelglistrasse 30
6390 Engelberg, Obwalden / CH
02 / Dittmann, Leander
Pl. du Vallon 18
1005 Lausanne, Vaud / CH
03 / Chaize, Adrien
Verger l'Ecuyer 11
2068 Hauterive, Neuchatel / CH
04 / Hoyer, Svend
Ch. de Champs-Fleuri 20
1022 Chavannes-près-Renens, Vaud / CH
 [2013/10]
Representative(s)Engelhard, Markus
Boehmert & Boehmert
Anwaltspartnerschaft mbB
Pettenkoferstrasse 22
80336 München / DE
[N/P]
Former [2013/10]Engelhard, Markus
Boehmert & Boehmert
Pettenkoferstrasse 20-22
80336 München / DE
Application number, filing date11007084.431.08.2011
[2013/10]
Filing languageEN
Procedural languageEN
PublicationType: A1 Application with search report 
No.:EP2564996
Date:06.03.2013
Language:EN
[2013/10]
Search report(s)(Supplementary) European search report - dispatched on:EP10.02.2012
ClassificationIPC:B26D5/00, B26F1/28, B23K26/38, B23K26/40, H01L21/00
[2013/10]
CPC:
B23K26/389 (EP,US); B23K26/38 (KR); H05K3/0085 (US);
B23K26/40 (EP,US); B26D5/00 (EP,KR,US); B26F1/28 (EP,KR,US);
B23K2103/50 (EP,US); Y10T29/49124 (EP,US) (-)
Designated contracting statesAL,   AT,   BE,   BG,   CH,   CY,   CZ,   DE,   DK,   EE,   ES,   FI,   FR,   GB,   GR,   HR,   HU,   IE,   IS,   IT,   LI,   LT,   LU,   LV,   MC,   MK,   MT,   NL,   NO,   PL,   PT,   RO,   RS,   SE,   SI,   SK,   SM,   TR [2013/10]
Extension statesBANot yet paid
MENot yet paid
TitleGerman:Verfahren zur Erzeugung eines Lochs oder einer Aussparung oder eines Wells in einem elektrisch isolierenden oder halbleitenden Substrat[2013/10]
English:A method of generating a hole or recess or well in an electrically insulating or semiconducting substrate[2013/10]
French:Procédé de génération d'orifice, enclave ou puits dans un substrat à isolation électrique ou semi-conducteur[2013/10]
Examination procedure12.08.2013Amendment by applicant (claims and/or description)
12.08.2013Examination requested  [2013/39]
22.03.2016Despatch of a communication from the examining division (Time limit: M04)
02.08.2016Application deemed to be withdrawn, date of legal effect  [2017/01]
26.08.2016Despatch of communication that the application is deemed to be withdrawn, reason: reply to the communication from the examining division not received in time  [2017/01]
Divisional application(s)The date of the Examining Division's first communication in respect of the earliest application for which a communication has been issued is  22.03.2016
Fees paidRenewal fee
19.08.2013Renewal fee patent year 03
13.08.2014Renewal fee patent year 04
10.08.2015Renewal fee patent year 05
Penalty fee
Additional fee for renewal fee
31.08.201606   M06   Not yet paid
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Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court.
Documents cited:Search[A]US2141869  (FRITZ KONIG) [A] 1-10 * the whole document *;
 [A]US2678373  (SURAN JEROME J) [A] 1-10 * the whole document *;
 [A]FR2203313  (GESTETNER LTD [GB]) [A] 1-10 * the whole document *;
 [A]GB1603515  (MOLINS LTD) [A] 1-10 * the whole document *;
 [A]DE10328937  (GROSSE WERNER [DE]) [A] 1-10 * the whole document *;
 [YD]WO2009059786  (PICODRILL SA [CH], et al) [YD] 1-10 * page 1 - page 25; figures 1-4 *;
 [A]US2011042132  (DITTMANN LEANDER [CH]) [A] 1-10* paragraph [0002] - paragraph [0071]; figures 1-9c *;
 [YD]WO2011038788  (PICODRILL SA [CH], et al) [YD] 1-10 * page 1 - page 18; figures 1-11B *;
 [Y]  - Bo Hanus, "Grundbausteine der Elektronik", Bo Hanus, Bo Hanus, Der leichte Einstieg in die Elektronik: ein leicht verständlicher Grundkurs mit vielen praktischen Bauanleitungen, D-85586 Poing, Franzis' Verlag, (19991231), pages 4-7 - 18-37, ISBN 3-7723-5544-7, XP055018026 [Y] 1-10 * page 4 - page 7 * * page 18 - page 37 *
by applicantWO2005097439
 WO2009059786
 WO2010063462
 WO2011038788
The EPO accepts no responsibility for the accuracy of data originating from other authorities; in particular, it does not guarantee that it is complete, up to date or fit for specific purposes.