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Extract from the Register of European Patents

EP About this file: EP2498398

EP2498398 - Amplifier circuit and method [Right-click to bookmark this link]
StatusNo opposition filed within time limit
Status updated on  04.09.2020
Database last updated on 03.09.2024
FormerThe patent has been granted
Status updated on  27.09.2019
FormerGrant of patent is intended
Status updated on  25.07.2019
FormerExamination is in progress
Status updated on  04.03.2017
Most recent event   Tooltip08.07.2022Lapse of the patent in a contracting state
New state(s): MK		published on 10.08.2022  [2022/32]
Applicant(s)For all designated states
NXP B.V.
High Tech Campus 60
5656 AG Eindhoven / NL
[2012/37]
Inventor(s)01 / Kasanyal, Sunil
c/o NXP Semiconductors
IP & L
Betchworth House
57-65 Station Road
Redhill Surrey RH1 1DL / GB
 [2012/37]
Representative(s)Hardingham, Christopher Mark
NXP Semiconductors
Intellectual Property Group
Abbey House
25 Clarendon Road
Redhill, Surrey RH1 1QZ / GB
[2019/44]
Former [2012/37]Hardingham, Christopher Mark
NXP Semiconductors
Intellectual Property and Licensing
Red Central
60 High Street, Redhill
Surrey RH1 1NY / GB
Application number, filing date11157160.007.03.2011
[2012/37]
Filing languageEN
Procedural languageEN
PublicationType: A1 Application with search report 
No.:EP2498398
Date:12.09.2012
Language:EN
[2012/37]
Type: B1 Patent specification 
No.:EP2498398
Date:30.10.2019
Language:EN
[2019/44]
Search report(s)(Supplementary) European search report - dispatched on:EP24.08.2011
ClassificationIPC:H03F3/45, H04L25/02, H03K5/003, H03K19/0185
[2012/37]
CPC:
H03F3/45192 (EP,US); H03F3/45632 (EP,US); H03K5/003 (EP,US);
H04L25/0292 (EP,US); H03F2200/408 (EP,US); H03F2200/516 (EP,US);
H03F2203/45101 (EP,US); H03F2203/45244 (EP,US); H03F2203/45482 (EP,US);
H03F2203/45652 (EP,US); H03F2203/45682 (EP,US); H03F2203/45702 (EP,US) (-)
Designated contracting statesAL,   AT,   BE,   BG,   CH,   CY,   CZ,   DE,   DK,   EE,   ES,   FI,   FR,   GB,   GR,   HR,   HU,   IE,   IS,   IT,   LI,   LT,   LU,   LV,   MC,   MK,   MT,   NL,   NO,   PL,   PT,   RO,   RS,   SE,   SI,   SK,   SM,   TR [2019/44]
Former [2012/37]AL,  AT,  BE,  BG,  CH,  CY,  CZ,  DE,  DK,  EE,  ES,  FI,  FR,  GB,  GR,  HR,  HU,  IE,  IS,  IT,  LI,  LT,  LU,  LV,  MC,  MK,  MT,  NL,  NO,  PL,  PT,  RO,  RS,  SE,  SI,  SK,  SM,  TR 
TitleGerman:Verstärkerschaltung und Verfahren[2012/37]
English:Amplifier circuit and method[2012/37]
French:Circuit amplificateur et procédé[2012/37]
Examination procedure12.09.2011Amendment by applicant (claims and/or description)
12.03.2013Examination requested  [2013/16]
18.04.2013Despatch of communication that the application is deemed to be withdrawn, reason: reply to the Extended European Search Report/Written Opinion of the International Searching Authority/International Preliminary Examination Report/Supplementary international search report not received in time
25.04.2013Request for decision received: Application is deemed to be withdrawn
03.05.2013Result of request for decision (Application is deemed to be withdrawn): Request accepted
20.04.2015Despatch of a communication from the examining division (Time limit: M04)
27.07.2015Reply to a communication from the examining division
22.02.2017Despatch of a communication from the examining division (Time limit: M06)
14.08.2017Reply to a communication from the examining division
26.07.2019Communication of intention to grant the patent
17.09.2019Fee for grant paid
17.09.2019Fee for publishing/printing paid
17.09.2019Receipt of the translation of the claim(s)
Divisional application(s)The date of the Examining Division's first communication in respect of the earliest application for which a communication has been issued is  20.04.2015
Opposition(s)31.07.2020No opposition filed within time limit [2020/41]
Fees paidRenewal fee
02.04.2013Renewal fee patent year 03
31.03.2014Renewal fee patent year 04
31.03.2015Renewal fee patent year 05
31.03.2016Renewal fee patent year 06
31.03.2017Renewal fee patent year 07
03.04.2018Renewal fee patent year 08
01.04.2019Renewal fee patent year 09
Opt-out from the exclusive  Tooltip
competence of the Unified
Patent Court		 See the Register of the Unified Patent Court for opt-out data
Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court.
Lapses during opposition  TooltipHU07.03.2011
AL30.10.2019
AT30.10.2019
CY30.10.2019
CZ30.10.2019
DK30.10.2019
EE30.10.2019
ES30.10.2019
FI30.10.2019
HR30.10.2019
IT30.10.2019
LT30.10.2019
LV30.10.2019
MC30.10.2019
MK30.10.2019
MT30.10.2019
NL30.10.2019
PL30.10.2019
RO30.10.2019
RS30.10.2019
SE30.10.2019
SI30.10.2019
SK30.10.2019
SM30.10.2019
TR30.10.2019
BG30.01.2020
NO30.01.2020
GR31.01.2020
IS29.02.2020
PT02.03.2020
GB07.03.2020
IE07.03.2020
LU07.03.2020
BE31.03.2020
CH31.03.2020
FR31.03.2020
LI31.03.2020
[2022/32]
Former [2022/27]HU07.03.2011
AL30.10.2019
AT30.10.2019
CY30.10.2019
CZ30.10.2019
DK30.10.2019
EE30.10.2019
ES30.10.2019
FI30.10.2019
HR30.10.2019
IT30.10.2019
LT30.10.2019
LV30.10.2019
MC30.10.2019
MT30.10.2019
NL30.10.2019
PL30.10.2019
RO30.10.2019
RS30.10.2019
SE30.10.2019
SI30.10.2019
SK30.10.2019
SM30.10.2019
TR30.10.2019
BG30.01.2020
NO30.01.2020
GR31.01.2020
IS29.02.2020
PT02.03.2020
GB07.03.2020
IE07.03.2020
LU07.03.2020
BE31.03.2020
CH31.03.2020
FR31.03.2020
LI31.03.2020
Former [2022/26]AL30.10.2019
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CZ30.10.2019
DK30.10.2019
EE30.10.2019
ES30.10.2019
FI30.10.2019
HR30.10.2019
IT30.10.2019
LT30.10.2019
LV30.10.2019
MC30.10.2019
NL30.10.2019
PL30.10.2019
RO30.10.2019
RS30.10.2019
SE30.10.2019
SI30.10.2019
SK30.10.2019
SM30.10.2019
TR30.10.2019
BG30.01.2020
NO30.01.2020
GR31.01.2020
IS29.02.2020
PT02.03.2020
GB07.03.2020
IE07.03.2020
LU07.03.2020
BE31.03.2020
CH31.03.2020
FR31.03.2020
LI31.03.2020
Former [2021/22]AL30.10.2019
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DK30.10.2019
EE30.10.2019
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FI30.10.2019
HR30.10.2019
IT30.10.2019
LT30.10.2019
LV30.10.2019
MC30.10.2019
NL30.10.2019
PL30.10.2019
RO30.10.2019
RS30.10.2019
SE30.10.2019
SI30.10.2019
SK30.10.2019
SM30.10.2019
BG30.01.2020
NO30.01.2020
GR31.01.2020
IS29.02.2020
PT02.03.2020
GB07.03.2020
IE07.03.2020
LU07.03.2020
BE31.03.2020
CH31.03.2020
FR31.03.2020
LI31.03.2020
Former [2021/12]AL30.10.2019
AT30.10.2019
CZ30.10.2019
DK30.10.2019
EE30.10.2019
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FI30.10.2019
HR30.10.2019
IT30.10.2019
LT30.10.2019
LV30.10.2019
MC30.10.2019
NL30.10.2019
PL30.10.2019
RO30.10.2019
RS30.10.2019
SE30.10.2019
SI30.10.2019
SK30.10.2019
SM30.10.2019
BG30.01.2020
NO30.01.2020
GR31.01.2020
IS29.02.2020
PT02.03.2020
IE07.03.2020
LU07.03.2020
BE31.03.2020
CH31.03.2020
FR31.03.2020
LI31.03.2020
Former [2021/07]AL30.10.2019
AT30.10.2019
CZ30.10.2019
DK30.10.2019
EE30.10.2019
ES30.10.2019
FI30.10.2019
HR30.10.2019
IT30.10.2019
LT30.10.2019
LV30.10.2019
MC30.10.2019
NL30.10.2019
PL30.10.2019
RO30.10.2019
RS30.10.2019
SE30.10.2019
SI30.10.2019
SK30.10.2019
SM30.10.2019
BG30.01.2020
NO30.01.2020
GR31.01.2020
IS29.02.2020
PT02.03.2020
IE07.03.2020
LU07.03.2020
CH31.03.2020
FR31.03.2020
LI31.03.2020
Former [2021/04]AL30.10.2019
AT30.10.2019
CZ30.10.2019
DK30.10.2019
EE30.10.2019
ES30.10.2019
FI30.10.2019
HR30.10.2019
IT30.10.2019
LT30.10.2019
LV30.10.2019
MC30.10.2019
NL30.10.2019
PL30.10.2019
RO30.10.2019
RS30.10.2019
SE30.10.2019
SI30.10.2019
SK30.10.2019
SM30.10.2019
BG30.01.2020
NO30.01.2020
GR31.01.2020
IS29.02.2020
PT02.03.2020
LU07.03.2020
Former [2020/51]AL30.10.2019
AT30.10.2019
CZ30.10.2019
DK30.10.2019
EE30.10.2019
ES30.10.2019
FI30.10.2019
HR30.10.2019
IT30.10.2019
LT30.10.2019
LV30.10.2019
MC30.10.2019
NL30.10.2019
PL30.10.2019
RO30.10.2019
RS30.10.2019
SE30.10.2019
SI30.10.2019
SK30.10.2019
SM30.10.2019
BG30.01.2020
NO30.01.2020
GR31.01.2020
IS29.02.2020
PT02.03.2020
Former [2020/49]AL30.10.2019
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DK30.10.2019
EE30.10.2019
ES30.10.2019
FI30.10.2019
HR30.10.2019
IT30.10.2019
LT30.10.2019
LV30.10.2019
MC30.10.2019
NL30.10.2019
PL30.10.2019
RO30.10.2019
RS30.10.2019
SE30.10.2019
SK30.10.2019
SM30.10.2019
BG30.01.2020
NO30.01.2020
GR31.01.2020
IS29.02.2020
PT02.03.2020
Former [2020/38]AL30.10.2019
CZ30.10.2019
DK30.10.2019
EE30.10.2019
ES30.10.2019
FI30.10.2019
HR30.10.2019
IT30.10.2019
LT30.10.2019
LV30.10.2019
NL30.10.2019
PL30.10.2019
RO30.10.2019
RS30.10.2019
SE30.10.2019
SK30.10.2019
SM30.10.2019
BG30.01.2020
NO30.01.2020
GR31.01.2020
IS29.02.2020
PT02.03.2020
Former [2020/37]AL30.10.2019
CZ30.10.2019
DK30.10.2019
EE30.10.2019
ES30.10.2019
FI30.10.2019
HR30.10.2019
LT30.10.2019
LV30.10.2019
NL30.10.2019
PL30.10.2019
RO30.10.2019
RS30.10.2019
SE30.10.2019
SK30.10.2019
SM30.10.2019
BG30.01.2020
NO30.01.2020
GR31.01.2020
IS29.02.2020
PT02.03.2020
Former [2020/36]AL30.10.2019
CZ30.10.2019
DK30.10.2019
EE30.10.2019
ES30.10.2019
FI30.10.2019
HR30.10.2019
LT30.10.2019
LV30.10.2019
NL30.10.2019
PL30.10.2019
RO30.10.2019
RS30.10.2019
SE30.10.2019
BG30.01.2020
NO30.01.2020
GR31.01.2020
IS29.02.2020
PT02.03.2020
Former [2020/35]AL30.10.2019
CZ30.10.2019
ES30.10.2019
FI30.10.2019
HR30.10.2019
LT30.10.2019
LV30.10.2019
NL30.10.2019
PL30.10.2019
RO30.10.2019
RS30.10.2019
SE30.10.2019
BG30.01.2020
NO30.01.2020
GR31.01.2020
IS29.02.2020
PT02.03.2020
Former [2020/32]AL30.10.2019
ES30.10.2019
FI30.10.2019
HR30.10.2019
LT30.10.2019
LV30.10.2019
NL30.10.2019
PL30.10.2019
RS30.10.2019
SE30.10.2019
BG30.01.2020
NO30.01.2020
GR31.01.2020
IS29.02.2020
PT02.03.2020
Former [2020/25]ES30.10.2019
FI30.10.2019
HR30.10.2019
LT30.10.2019
LV30.10.2019
NL30.10.2019
PL30.10.2019
RS30.10.2019
SE30.10.2019
BG30.01.2020
NO30.01.2020
GR31.01.2020
IS29.02.2020
PT02.03.2020
Former [2020/24]ES30.10.2019
FI30.10.2019
LT30.10.2019
LV30.10.2019
NL30.10.2019
PL30.10.2019
SE30.10.2019
BG30.01.2020
NO30.01.2020
GR31.01.2020
IS29.02.2020
PT02.03.2020
Former [2020/23]ES30.10.2019
FI30.10.2019
LT30.10.2019
LV30.10.2019
NL30.10.2019
PL30.10.2019
SE30.10.2019
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NO30.01.2020
GR31.01.2020
PT02.03.2020
Former [2020/22]FI30.10.2019
LT30.10.2019
SE30.10.2019
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Former [2020/21]NO30.01.2020
Documents cited:Search[YD]US6930530  (WANG WEN-TAI [TW]) [YD] 7-11,13 * column 3, line 4 - column 4, line 15; figure 4 *;
 [A]US2006214692  (MOON HONG S [KR]) [A] 1-15 * paragraphs [0055] - [0083]; figures 6,7 *
 [XY]  - ANDREA BONI ET AL, "LVDS I/O Interface for Gb/s-per-Pin Operation in 0.35-m CMOS", IEEE JOURNAL OF SOLID-STATE CIRCUITS, IEEE SERVICE CENTER, PISCATAWAY, NJ, USA, (20010401), vol. 36, no. 4, ISSN 0018-9200, XP011061486 [X] 1,2,6,12,14,15 * page 708, column r, line 10 - page 709, column r, line 14; figures 4,5 * [Y] 7-11,13
 [A]  - KUMRIC M ET AL, "Digitally tuneable on-chip line termination resistor for 2.5Gbit/s LVDS receiver in 0.25[micro] standard CMOS technology", SOLID-STATE CIRCUITS CONFERENCE, 2001. ESSCIRC 2001. PROCEEDINGS OF TH E 27TH EUROPEAN VILLACH, AUSTRIA 18-20 SEPT. 2001, PISCATAWAY, NJ, USA,IEEE, (20010918), ISBN 978-2-914601-00-9, pages 241 - 244, XP010823744 [A] 1-15 * page 243, column L, lines 8-20; figure 6 *
ExaminationUS6956436
 US2004080368
by applicantUS6930530
The EPO accepts no responsibility for the accuracy of data originating from other authorities; in particular, it does not guarantee that it is complete, up to date or fit for specific purposes.