EP2386962 - Programmable queue structures for multiprocessors [Right-click to bookmark this link] | Status | No opposition filed within time limit Status updated on 06.02.2015 Database last updated on 19.10.2024 | Most recent event Tooltip | 12.10.2018 | Lapse of the patent in a contracting state New state(s): AL | published on 14.11.2018 [2018/46] | Applicant(s) | For all designated states Telefonaktiebolaget LM Ericsson (publ) 164 83 Stockholm / SE | [N/P] |
Former [2011/46] | For all designated states Telefonaktiebolaget L M Ericsson (Publ) 164 83 Stockholm / SE | Inventor(s) | 01 /
Gewirtz, Evan 2687 Paige Way San Ramon, CA 94582 / US | 02 /
Hathaway, Robert 788 Grape Avenue Sunnyvale, CA 94087 / US | 03 /
Meier, Stephan 2130 Via Escalera Los Altos, CA 94024 / US | [2011/46] | Representative(s) | Rees, Simon John Lewis Haseltine Lake LLP Redcliff Quay 120 Redcliff Street Bristol BS1 6HU / GB | [2014/14] |
Former [2011/46] | Rees, Simon John Lewis Haseltine Lake LLP Redcliff Quay 120 Redcliff Street Bristol, Avon BS1 6HU / GB | Application number, filing date | 11164626.1 | 03.05.2011 | [2011/46] | Priority number, date | US20100777084 | 10.05.2010 Original published format: US 777084 | [2011/46] | Filing language | EN | Procedural language | EN | Publication | Type: | A1 Application with search report | No.: | EP2386962 | Date: | 16.11.2011 | Language: | EN | [2011/46] | Type: | B1 Patent specification | No.: | EP2386962 | Date: | 02.04.2014 | Language: | EN | [2014/14] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 30.09.2011 | Classification | IPC: | G06F15/167 | [2011/46] | CPC: |
G06F9/544 (EP,US);
G06F9/52 (EP,US)
| Designated contracting states | AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LI, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR [2011/46] | Title | German: | Programmierbare Warteschlangenstrukturen für Multiprozessoren | [2011/46] | English: | Programmable queue structures for multiprocessors | [2011/46] | French: | Structures programmables de file d'attente pour multiprocesseurs | [2011/46] | Examination procedure | 04.05.2012 | Amendment by applicant (claims and/or description) | 04.05.2012 | Examination requested [2012/24] | 11.06.2012 | Despatch of a communication from the examining division (Time limit: M06) | 29.01.2013 | Despatch of communication that the application is deemed to be withdrawn, reason: reply to the communication from the examining division not received in time | 27.03.2013 | Reply to a communication from the examining division | 08.05.2013 | Despatch of a communication from the examining division (Time limit: M04) | 27.08.2013 | Reply to a communication from the examining division | 21.10.2013 | Communication of intention to grant the patent | 17.02.2014 | Fee for grant paid | 17.02.2014 | Fee for publishing/printing paid | Divisional application(s) | The date of the Examining Division's first communication in respect of the earliest application for which a communication has been issued is 11.06.2012 | Opposition(s) | 06.01.2015 | No opposition filed within time limit [2015/11] | Request for further processing for: | The application is deemed to be withdrawn due to failure to reply to the examination report | 27.03.2013 | Request for further processing filed | 27.03.2013 | Full payment received (date of receipt of payment) Request granted | 09.04.2013 | Decision despatched | Fees paid | Renewal fee | 28.05.2013 | Renewal fee patent year 03 |
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Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Lapses during opposition Tooltip | HU | 03.05.2011 | AL | 02.04.2014 | AT | 02.04.2014 | BE | 02.04.2014 | CY | 02.04.2014 | CZ | 02.04.2014 | DK | 02.04.2014 | EE | 02.04.2014 | ES | 02.04.2014 | FI | 02.04.2014 | HR | 02.04.2014 | IT | 02.04.2014 | LT | 02.04.2014 | LV | 02.04.2014 | MC | 02.04.2014 | MK | 02.04.2014 | MT | 02.04.2014 | NL | 02.04.2014 | PL | 02.04.2014 | RO | 02.04.2014 | SE | 02.04.2014 | SI | 02.04.2014 | SK | 02.04.2014 | SM | 02.04.2014 | TR | 02.04.2014 | IE | 03.05.2014 | LU | 03.05.2014 | CH | 31.05.2014 | LI | 31.05.2014 | FR | 02.06.2014 | BG | 02.07.2014 | NO | 02.07.2014 | GR | 03.07.2014 | IS | 02.08.2014 | PT | 04.08.2014 | RS | 19.11.2014 | [2018/46] |
Former [2018/31] | HU | 03.05.2011 | |
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Former [2014/47] | CY | 02.04.2014 | Documents cited: | Search | [I] - SU S-C ET AL, "A memory-mapped interprocessor communication architecture using FIFO RAMs", MICROPROCESSING AND MICROPROGRAMMING, ELSEVIER SCIENCE PUBLISHERS, BV., AMSTERDAM, NL, vol. 34, no. 1-5, doi:10.1016/0165-6074(92)90131-P, ISSN 0165-6074, (19920201), pages 187 - 191, (19920201), XP024233494 [I] 1-19 * Sections 1, 2, 3 and 3.1;; figures 3-5 * DOI: http://dx.doi.org/10.1016/0165-6074(92)90131-P | [A] - MATTHIAS BLUMRICH ET AL, "Virtual-Memory-Mapped Network Interfaces", IEEE MICRO, (19950201), vol. 15, no. 1, doi:10.1109/40.342014, ISSN 0272-1732, pages 21 - 28, XP055007890 [A] 1-19 * Introduction and section titled "SHRIMP -I network interface" * DOI: http://dx.doi.org/10.1109/40.342014 |