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Extract from the Register of European Patents

EP About this file: EP2610898

EP2610898 - METHOD FOR FABRICATING EPITAXIAL SUBSTRATE FOR SEMICONDUCTOR DEVICE, AND METHOD FOR FABRICATING SEMICONDUCTOR DEVICE [Right-click to bookmark this link]
Former [2013/27]EPITAXIAL SUBSTRATE FOR SEMICONDUCTOR ELEMENT, SEMICONDUCTOR ELEMENT, METHOD FOR FABRICATING EPITAXIAL SUBSTRATE FOR SEMICONDUCTOR ELEMENT, AND METHOD FOR FABRICATING SEMICONDUCTOR ELEMENT
[2020/24]
StatusNo opposition filed within time limit
Status updated on  01.10.2021
Database last updated on 05.08.2024
FormerThe patent has been granted
Status updated on  23.10.2020
FormerGrant of patent is intended
Status updated on  08.06.2020
FormerExamination is in progress
Status updated on  23.10.2017
Most recent event   Tooltip14.06.2024Lapse of the patent in a contracting state
New state(s): TR		published on 17.07.2024  [2024/29]
Applicant(s)For all designated states
NGK Insulators, Ltd.
2-56, Suda-cho Mizuho-ku
Nagoya-shi, Aichi 467-8530 / JP
[2013/27]
Inventor(s)01 / MIYOSHI, Makoto
1-11-33, Konomiya
Inazawa-shi, Aichi 492-8137 / JP
02 / ICHIMURA, Mikiya
c/o NGK INSULATORS LTD.
2-56, Suda-cho
Mizuho-ku
Nagoya-shi, Aichi 467-8530 / JP
03 / TANAKA, Mitsuhiro
3-7-21, Kasuga
Tsukuba-shi, Ibaraki 3050821 / JP
 [2015/14]
Former [2013/27]01 / MIYOSHI Makoto
1-11-33, Konomiya
Inazawa-shi Aichi 492-8137 / JP
02 / ICHIMURA Mikiya
c/o NGK INSULATORS LTD.
2-56, Suda-cho
Mizuho-ku
Nagoya-shi Aichi 467-8530 / JP
03 / TANAKA Mitsuhiro
3-7-21, Kasuga
Tsukuba-shi, Ibaraki 3050821 / JP
Representative(s)Mewburn Ellis LLP
Aurora Building
Counterslip
Bristol BS1 6BX / GB
[2020/48]
Former [2013/27]Naylor, Matthew John
Mewburn Ellis LLP
33 Gutter Lane
London
EC2V 8AS / GB
Application number, filing date11819859.719.08.2011
[2020/48]
WO2011JP68742
Priority number, dateJP2010018789925.08.2010         Original published format: JP 2010187899
[2013/27]
Filing languageJA
Procedural languageEN
PublicationType: A1 Application with search report
No.:WO2012026396
Date:01.03.2012
Language:JA
[2012/09]
Type: A1 Application with search report 
No.:EP2610898
Date:03.07.2013
Language:EN
[2013/27]
Type: B1 Patent specification 
No.:EP2610898
Date:25.11.2020
Language:EN
[2020/48]
Search report(s)International search report - published on:JP01.03.2012
(Supplementary) European search report - dispatched on:EP18.07.2014
ClassificationIPC:H01L29/778, H01L21/336, H01L21/02, // H01L29/20, H01L29/205
[2014/34]
CPC:
H01L29/66462 (EP,US); H01L29/778 (US); H01L29/66431 (US);
H01L29/7786 (EP,US); H01L29/7787 (US); H01L21/0237 (EP,US);
H01L21/02378 (EP,US); H01L21/02458 (EP,US); H01L21/0254 (EP,US);
H01L21/0262 (EP,US); H01L29/2003 (EP,US); H01L29/205 (EP,US) (-)
Former IPC [2013/27]H01L21/338, H01L21/205, H01L29/778, H01L29/812
Designated contracting statesAL,   AT,   BE,   BG,   CH,   CY,   CZ,   DE,   DK,   EE,   ES,   FI,   FR,   GB,   GR,   HR,   HU,   IE,   IS,   IT,   LI,   LT,   LU,   LV,   MC,   MK,   MT,   NL,   NO,   PL,   PT,   RO,   RS,   SE,   SI,   SK,   SM,   TR [2013/27]
Extension statesBANot yet paid
MENot yet paid
TitleGerman:VERFAHREN ZUR HERSTELLUNG EINES EPITAKTISCHEN SUBSTRATS FÜR EIN HALBLEITERBAUELEMENT UND VERFAHREN ZUR HERSTELLUNG DES HALBLEITERBAUELEMENTS[2020/24]
English:METHOD FOR FABRICATING EPITAXIAL SUBSTRATE FOR SEMICONDUCTOR DEVICE, AND METHOD FOR FABRICATING SEMICONDUCTOR DEVICE[2020/24]
French:PROCÉDÉ DE FABRICATION D'UN SUBSTRAT ÉPITAXIAL POUR UN DISPOSITIF SEMI-CONDUCTEUR, ET PROCÉDÉ DE FABRICATION DU DISPOSITIF SEMI-CONDUCTEUR[2020/24]
Former [2013/27]EPITAKTISCHES SUBSTRAT FÜR EIN HALBLEITERELEMENT, HALBLEITERELEMENT, VERFAHREN ZUR HERSTELLUNG DES EPITAKTISCHEN SUBSTRATS FÜR EIN HALBLEITERELEMENT UND VERFAHREN ZUR HERSTELLUNG DES HALBLEITERELEMENTS
Former [2013/27]EPITAXIAL SUBSTRATE FOR SEMICONDUCTOR ELEMENT, SEMICONDUCTOR ELEMENT, METHOD FOR FABRICATING EPITAXIAL SUBSTRATE FOR SEMICONDUCTOR ELEMENT, AND METHOD FOR FABRICATING SEMICONDUCTOR ELEMENT
Former [2013/27]SUBSTRAT ÉPITAXIAL POUR ÉLÉMENT SEMI-CONDUCTEUR, ÉLÉMENT SEMI-CONDUCTEUR, PROCÉDÉ DE FABRICATION DE SUBSTRAT ÉPITAXIAL POUR ÉLÉMENT SEMI-CONDUCTEUR, ET PROCÉDÉ DE FABRICATION D'ÉLÉMENT SEMI-CONDUCTEUR
Entry into regional phase21.02.2013Translation filed 
21.02.2013National basic fee paid 
21.02.2013Search fee paid 
21.02.2013Designation fee(s) paid 
21.02.2013Examination fee paid 
Examination procedure21.02.2013Examination requested  [2013/27]
13.02.2015Amendment by applicant (claims and/or description)
31.03.2015Despatch of a communication from the examining division (Time limit: M04)
10.08.2015Reply to a communication from the examining division
12.10.2017Despatch of a communication from the examining division (Time limit: M04)
21.02.2018Reply to a communication from the examining division
09.06.2020Communication of intention to grant the patent
15.10.2020Fee for grant paid
15.10.2020Fee for publishing/printing paid
15.10.2020Receipt of the translation of the claim(s)
Divisional application(s)The date of the Examining Division's first communication in respect of the earliest application for which a communication has been issued is  31.03.2015
Opposition(s)26.08.2021No opposition filed within time limit [2021/44]
Fees paidRenewal fee
20.08.2013Renewal fee patent year 03
26.08.2014Renewal fee patent year 04
24.08.2015Renewal fee patent year 05
24.08.2016Renewal fee patent year 06
25.08.2017Renewal fee patent year 07
10.08.2018Renewal fee patent year 08
15.08.2019Renewal fee patent year 09
13.08.2020Renewal fee patent year 10
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Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court.
Lapses during opposition  TooltipHU19.08.2011
AL25.11.2020
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GR26.02.2021
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[2024/29]
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GB19.08.2021
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BG25.02.2021
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GB19.08.2021
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LU19.08.2021
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GR26.02.2021
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GR26.02.2021
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LU19.08.2021
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GR26.02.2021
IS25.03.2021
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RO25.11.2020
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SM25.11.2020
BG25.02.2021
NO25.02.2021
GR26.02.2021
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SK25.11.2020
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Documents cited:Search[Y]EP1612866  (IMEC INTER UNI MICRO ELECTR [BE]) [Y] 1-13 * figure 1 * * paragraphs [0046] , [0 48] , [0 82] , [0 83] , [ 102] , [ 154] , [ 177] *;
 [A]JP2008084942  (OKI ELECTRIC IND CO LTD) [A] 2,3,8,9 * figure 1 * * abstract ** paragraph [0021] *;
 [YD]WO2009119357  (NGK INSULATORS LTD [JP], et al) [YD] 1-13 * paragraphs [0009] - [0013] - [0 71] , [0 82] , [ 116] * * figures 1-7 and associated text *;
 [P]EP2259287  (NGK INSULATORS LTD [JP])
International search[Y]WO03032397  (CREE LIGHTING CO [US]);
 [Y]JP2006024927  (IMEC INTER UNI MICRO ELECTR);
 [Y]WO2009119357  (NGK INSULATORS LTD [JP], et al);
 [Y]JP2009302370  (NIPPON TELEGRAPH & TELEPHONE);
 [A]JP2010045343  (IMEC)
by applicantWO2009119357
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    - HIROSHI KAMBAYASHI; YOSHIHIRO SATOH; SHINYA OOMOTO; TAKUYA KOKAWA; TAKEHIRO NOMURA; SADAHIRO KATO; TAT-SING PAWL CHOW, "Over 100A Operation normally-off AlGaN/GaN hybrid MOS-HFET on Si substrate with high-breakdown voltage", SOLID-STATE ELECTRONICS, (2010), vol. 54, pages 660 - 664, XP026994157
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