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Extract from the Register of European Patents

EP About this file: EP2595176

EP2595176 - LATTICE-MISMATCHED SEMICONDUCTOR STRUCTURES WITH REDUCED DISLOCATION DEFECT DENSITIES AND RELATED METHODS FOR DEVICE FABRICATION [Right-click to bookmark this link]
Former [2013/21]Lattice-mismatched semiconductor structures with reduced dislocation defect densities related methods for device fabrication
[2019/34]
StatusNo opposition filed within time limit
Status updated on  06.11.2020
Database last updated on 24.07.2024
FormerThe patent has been granted
Status updated on  05.12.2019
FormerGrant of patent is intended
Status updated on  25.07.2019
FormerExamination is in progress
Status updated on  17.07.2019
Most recent event   Tooltip24.06.2022Lapse of the patent in a contracting state
New state(s): CY, HU		published on 27.07.2022  [2022/30]
Applicant(s)For all designated states
Taiwan Semiconductor Manufacturing Company, Ltd.
No.8, Li-Hsin Road 6, Science-Based Industrial Park Hsin-Chu
300-77 / TW
[2013/21]
Inventor(s)01 / Cheng, Zhiyuan
247 Sandy Pond Road
Lincoln, MA 01773 / US
02 / Currie, Matthew T.
7 Regent Circle Nr. 4
Brookline, MA 02445 / US
03 / Lochtefeld, Anthony J.
121 Little Neck Road
Ipswich, MA 01938 / US
04 / Fiorenza, James
26 High Street
Wilmington, MA 01887 / US
05 / Langdo, Thomas A.
11 Lilac Court
Cambridge, MA 02141 / US
06 / Braithwaite, Glyn
22 Middle Green
Whitley Bay, Tyne and Wear NE25 9SF / GB
 [2013/21]
Representative(s)HGF
HGF Limited
1 City Walk
Leeds LS11 9DX / GB
[N/P]
Former [2020/01]HGF Limited
1 City Walk
Leeds LS11 9DX / GB
Former [2013/30]Atkinson, Jonathan David Mark, et al
Harrison Goddard Foote LLP
Belgrave Hall
Belgrave Street
Leeds LS2 8DD / GB
Former [2013/21]Harrison Goddard Foote LLP
Belgrave Hall
Belgrave Street
Leeds
LS2 8DD / GB
Application number, filing date13155284.617.05.2006
[2013/21]
Priority number, dateUS20050681940P17.05.2005         Original published format: US 681940 P
[2013/21]
Filing languageEN
Procedural languageEN
PublicationType: A2 Application without search report 
No.:EP2595176
Date:22.05.2013
Language:EN
[2013/21]
Type: A3 Search report 
No.:EP2595176
Date:17.07.2013
Language:EN
[2013/29]
Type: B1 Patent specification 
No.:EP2595176
Date:01.01.2020
Language:EN
[2020/01]
Search report(s)(Supplementary) European search report - dispatched on:EP18.06.2013
ClassificationIPC:H01L21/20, H01L21/02, // H01L29/66, H01L29/78, H01L21/762
[2013/29]
CPC:
H01L21/02647 (EP,US); H01L21/20 (KR); H01L21/02381 (EP,US);
H01L21/0245 (EP,US); H01L21/0251 (EP,US); H01L21/02521 (EP,US);
H01L21/02532 (EP,US); H01L21/0254 (EP,US); H01L21/02639 (EP,US);
H01L21/8258 (EP,US); H01L21/7624 (EP,US); H01L29/66795 (EP,US);
H01L29/785 (EP,US) (-)
Former IPC [2013/21]H01L21/20, H01L21/02
Designated contracting statesAT,   BE,   BG,   CH,   CY,   CZ,   DE,   DK,   EE,   ES,   FI,   FR,   GB,   GR,   HU,   IE,   IS,   IT,   LI,   LT,   LU,   LV,   MC,   NL,   PL,   PT,   RO,   SE,   SI,   SK,   TR [2020/01]
Former [2013/21]AT,  BE,  BG,  CH,  CY,  CZ,  DE,  DK,  EE,  ES,  FI,  FR,  GB,  GR,  HU,  IE,  IS,  IT,  LI,  LT,  LU,  LV,  MC,  NL,  PL,  PT,  RO,  SE,  SI,  SK,  TR 
TitleGerman:HALBLEITERSTRUKTUREN MIT GITTERFEHLANPASSUNG UND VERMINDERTER VERSETZUNGSFEHLERDICHTE SOWIE VERFAHREN ZUR BAUELEMENTHERSTELLUNG[2019/34]
English:LATTICE-MISMATCHED SEMICONDUCTOR STRUCTURES WITH REDUCED DISLOCATION DEFECT DENSITIES AND RELATED METHODS FOR DEVICE FABRICATION[2019/34]
French:STRUCTURES SEMI-CONDUCTRICES AVEC INEGALITES SUR LES PARAMETRES DE MAILLE ET POSSEDANT DES DENSITES DE DISLOCATIONS REDUITES ET PROCEDES DE FABRICATION DUDIT DISPOSITIF[2019/28]
Former [2013/21]Halbleiterstrukturen mit Gitterfehlanpassung und verminderter Versetzungsfehlerdichte sowie Verfahren zur Bauelementeherstellung
Former [2013/21]Lattice-mismatched semiconductor structures with reduced dislocation defect densities related methods for device fabrication
Former [2013/21]Structures semi-conductrices avec inegalites sur les parametres de maille et possedant des densites de dislocations reduites et procedes de fabrication dudit dispositif
Examination procedure16.10.2013Amendment by applicant (claims and/or description)
16.10.2013Examination requested  [2013/48]
10.02.2016Despatch of a communication from the examining division (Time limit: M04)
08.06.2016Reply to a communication from the examining division
29.05.2019Cancellation of oral proceeding that was planned for 03.06.2019
03.06.2019Date of oral proceedings (cancelled)
26.07.2019Communication of intention to grant the patent
22.11.2019Fee for grant paid
22.11.2019Fee for publishing/printing paid
22.11.2019Receipt of the translation of the claim(s)
Parent application(s)   TooltipEP06770525.1  / EP1882268
Divisional application(s)The date of the Examining Division's first communication in respect of the earliest application for which a communication has been issued (EP20060770525) is  17.02.2011
Opposition(s)02.10.2020No opposition filed within time limit [2020/50]
Fees paidRenewal fee
14.03.2013Renewal fee patent year 03
14.03.2013Renewal fee patent year 04
14.03.2013Renewal fee patent year 05
14.03.2013Renewal fee patent year 06
14.03.2013Renewal fee patent year 07
20.03.2013Renewal fee patent year 08
03.03.2014Renewal fee patent year 09
01.04.2015Renewal fee patent year 10
09.05.2016Renewal fee patent year 11
08.05.2017Renewal fee patent year 12
19.03.2018Renewal fee patent year 13
23.04.2019Renewal fee patent year 14
Opt-out from the exclusive  Tooltip
competence of the Unified
Patent Court		 See the Register of the Unified Patent Court for opt-out data
Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court.
Lapses during opposition  TooltipHU17.05.2006
AT01.01.2020
CY01.01.2020
CZ01.01.2020
DK01.01.2020
EE01.01.2020
ES01.01.2020
FI01.01.2020
IT01.01.2020
LT01.01.2020
LV01.01.2020
MC01.01.2020
NL01.01.2020
PL01.01.2020
RO01.01.2020
SE01.01.2020
SI01.01.2020
SK01.01.2020
TR01.01.2020
BG01.04.2020
GR02.04.2020
IS01.05.2020
GB17.05.2020
IE17.05.2020
LU17.05.2020
PT27.05.2020
BE31.05.2020
CH31.05.2020
FR31.05.2020
LI31.05.2020
[2022/27]
Former [2022/26]AT01.01.2020
CZ01.01.2020
DK01.01.2020
EE01.01.2020
ES01.01.2020
FI01.01.2020
IT01.01.2020
LT01.01.2020
LV01.01.2020
MC01.01.2020
NL01.01.2020
PL01.01.2020
RO01.01.2020
SE01.01.2020
SI01.01.2020
SK01.01.2020
TR01.01.2020
BG01.04.2020
GR02.04.2020
IS01.05.2020
GB17.05.2020
IE17.05.2020
LU17.05.2020
PT27.05.2020
BE31.05.2020
CH31.05.2020
FR31.05.2020
LI31.05.2020
Former [2021/23]AT01.01.2020
CZ01.01.2020
DK01.01.2020
EE01.01.2020
ES01.01.2020
FI01.01.2020
IT01.01.2020
LT01.01.2020
LV01.01.2020
MC01.01.2020
NL01.01.2020
PL01.01.2020
RO01.01.2020
SE01.01.2020
SI01.01.2020
SK01.01.2020
BG01.04.2020
GR02.04.2020
IS01.05.2020
GB17.05.2020
IE17.05.2020
LU17.05.2020
PT27.05.2020
BE31.05.2020
CH31.05.2020
FR31.05.2020
LI31.05.2020
Former [2021/22]AT01.01.2020
CZ01.01.2020
DK01.01.2020
EE01.01.2020
ES01.01.2020
FI01.01.2020
IT01.01.2020
LT01.01.2020
LV01.01.2020
MC01.01.2020
NL01.01.2020
PL01.01.2020
RO01.01.2020
SE01.01.2020
SI01.01.2020
SK01.01.2020
BG01.04.2020
GR02.04.2020
IS01.05.2020
GB17.05.2020
IE17.05.2020
LU17.05.2020
PT27.05.2020
CH31.05.2020
LI31.05.2020
Former [2021/20]AT01.01.2020
CZ01.01.2020
DK01.01.2020
EE01.01.2020
ES01.01.2020
FI01.01.2020
IT01.01.2020
LT01.01.2020
LV01.01.2020
MC01.01.2020
NL01.01.2020
PL01.01.2020
RO01.01.2020
SE01.01.2020
SI01.01.2020
SK01.01.2020
BG01.04.2020
GR02.04.2020
IS01.05.2020
IE17.05.2020
LU17.05.2020
PT27.05.2020
CH31.05.2020
LI31.05.2020
Former [2021/15]AT01.01.2020
CZ01.01.2020
DK01.01.2020
EE01.01.2020
ES01.01.2020
FI01.01.2020
IT01.01.2020
LT01.01.2020
LV01.01.2020
MC01.01.2020
NL01.01.2020
PL01.01.2020
RO01.01.2020
SE01.01.2020
SI01.01.2020
SK01.01.2020
BG01.04.2020
GR02.04.2020
IS01.05.2020
LU17.05.2020
PT27.05.2020
CH31.05.2020
LI31.05.2020
Former [2021/10]AT01.01.2020
CZ01.01.2020
DK01.01.2020
EE01.01.2020
ES01.01.2020
FI01.01.2020
IT01.01.2020
LT01.01.2020
LV01.01.2020
MC01.01.2020
NL01.01.2020
PL01.01.2020
RO01.01.2020
SE01.01.2020
SI01.01.2020
SK01.01.2020
BG01.04.2020
GR02.04.2020
IS01.05.2020
PT27.05.2020
CH31.05.2020
LI31.05.2020
Former [2021/08]CZ01.01.2020
DK01.01.2020
EE01.01.2020
ES01.01.2020
FI01.01.2020
LT01.01.2020
LV01.01.2020
NL01.01.2020
RO01.01.2020
SE01.01.2020
SK01.01.2020
BG01.04.2020
GR02.04.2020
IS01.05.2020
PT27.05.2020
CH31.05.2020
LI31.05.2020
Former [2020/50]CZ01.01.2020
DK01.01.2020
EE01.01.2020
ES01.01.2020
FI01.01.2020
LT01.01.2020
LV01.01.2020
NL01.01.2020
RO01.01.2020
SE01.01.2020
SK01.01.2020
BG01.04.2020
GR02.04.2020
IS01.05.2020
PT27.05.2020
Former [2020/49]CZ01.01.2020
DK01.01.2020
ES01.01.2020
FI01.01.2020
LT01.01.2020
LV01.01.2020
NL01.01.2020
RO01.01.2020
SE01.01.2020
SK01.01.2020
BG01.04.2020
GR02.04.2020
IS01.05.2020
PT27.05.2020
Former [2020/48]CZ01.01.2020
DK01.01.2020
ES01.01.2020
FI01.01.2020
LT01.01.2020
LV01.01.2020
NL01.01.2020
RO01.01.2020
SE01.01.2020
BG01.04.2020
GR02.04.2020
IS01.05.2020
PT27.05.2020
Former [2020/47]CZ01.01.2020
DK01.01.2020
ES01.01.2020
FI01.01.2020
LT01.01.2020
LV01.01.2020
NL01.01.2020
SE01.01.2020
BG01.04.2020
GR02.04.2020
IS01.05.2020
PT27.05.2020
Former [2020/40]CZ01.01.2020
FI01.01.2020
LT01.01.2020
LV01.01.2020
NL01.01.2020
SE01.01.2020
BG01.04.2020
GR02.04.2020
IS01.05.2020
PT27.05.2020
Former [2020/39]CZ01.01.2020
FI01.01.2020
LT01.01.2020
LV01.01.2020
NL01.01.2020
SE01.01.2020
BG01.04.2020
GR02.04.2020
PT27.05.2020
Former [2020/38]CZ01.01.2020
FI01.01.2020
LT01.01.2020
LV01.01.2020
NL01.01.2020
SE01.01.2020
GR02.04.2020
PT27.05.2020
Former [2020/36]CZ01.01.2020
FI01.01.2020
LT01.01.2020
NL01.01.2020
PT27.05.2020
Former [2020/35]CZ01.01.2020
FI01.01.2020
LT01.01.2020
NL01.01.2020
Former [2020/33]NL01.01.2020
Documents cited:Search[YD]US5221413  (BRASEN DANIEL [US], et al) [YD] 1-10* claim 1 *;
 [YD]  - LANGDO ET AL., "High Quality Ge on Si by Epitaxial Necking", APPLIED PHYSICS LETTERS, (200004), vol. 76, no. 25, XP002698257 [YD] 1-10 * page 3700, column r - page 3701, column l; figure 1 *

DOI:   http://dx.doi.org/10.1063/1.126754
ExaminationUS2002066403
    - NAM OK-HYUN ET AL, "Lateral epitaxy of low defect density GaN layers via organometallic vapor phase epitaxy", APPLIED PHYSICS LETTERS, A I P PUBLISHING LLC, US, (19971103), vol. 71, no. 18, doi:10.1063/1.120164, ISSN 0003-6951, pages 2638 - 2640, XP012018948

DOI:   http://dx.doi.org/10.1063/1.120164
by applicantUS5221413
 US2004045499
    - CHOI, "Monolithic Integration of Si MOSFET's and GaAs MESFET's", IEEE ELECTRON DEVICE LETTERS, (198604), vol. EDL-7, no. 4
    - CHOI ET AL., "Monolithic Integration of GaAs/A[GaAs Double-Heterostructure LED's and Si MOSFET's", IEEE ELECTRON DEVICE LETTERS, (198609), vol. EDL-7, no. 9
    - SHICHIJO ET AL., "Co-Integration of GaAs MESFET and Si CMOS Circuits", IEEE ELECTRON DEVICE LETTERS, (198809), vol. 9, no. 9, doi:doi:10.1109/55.6940, XP000004018

DOI:   http://dx.doi.org/10.1109/55.6940
    - CHOI ET AL., "Monolithic Integration of GaAs/A[GaAs LED and Si Driver Circuit", IEEE ELECTRON DEVICE LETTERS, (198810), vol. 9, no. 10, doi:doi:10.1109/55.17828, page 513, XP000005119

DOI:   http://dx.doi.org/10.1109/55.17828
    - LANGDO ET AL., "High Quality Ge on Si by Epitaxial Necking", APPLIED PHYSICS LETTERS, (200004), vol. 76, no. 25, doi:doi:10.1063/1.126754, XP002698257

DOI:   http://dx.doi.org/10.1063/1.126754
    - WENCHONG HU ET AL., "Growth of well-aligned carbon nanotube arrays on silicon substrates using porous alumina film as a nanotemplate", APPLIED PHYSICS LETTERS, (2001), vol. 79, no. 19, doi:doi:10.1063/1.1415406, XP012029311

DOI:   http://dx.doi.org/10.1063/1.1415406
 US20040000566
The EPO accepts no responsibility for the accuracy of data originating from other authorities; in particular, it does not guarantee that it is complete, up to date or fit for specific purposes.