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EP2685500
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EP About this file: EP2685500
| EP2685500 - Integrated circuit on SOI comprising a thyristor (SCR) protecting against electrostatic discharges [Right-click to bookmark this link] | Status | The application is deemed to be withdrawn Status updated on 17.07.2015 Database last updated on 03.10.2024 | Most recent event Tooltip | 17.07.2015 | Application deemed to be withdrawn | published on 19.08.2015 [2015/34] | Applicant(s) | For all designated states Commissariat à l'Énergie Atomique et aux Énergies Alternatives Bâtiment "Le Ponant D" 25, Rue Leblanc 75015 Paris / FR | For all designated states STmicroelectronics SA 29, boulevard Romain Rolland 92120 Montrouge / FR | [N/P] |
| Former [2014/03] | For all designated states Commissariat à l'Énergie Atomique et aux Énergies Alternatives Bâtiment "Le Ponant D" 25, rue Leblanc 75015 Paris / FR | ||
| For all designated states STmicroelectronics SA 29, boulevard Romain Rolland 92120 Montrouge / FR | Inventor(s) | 01 /
Fenouillet-Beranger, Claire 55 rue de Mortillet 38000 GRENOBLE / FR | 02 /
Fonteneau, Pascal Les Glapigneux 38570 THEYS / FR | [2014/03] | Representative(s) | Guérin, Jean-Philippe, et al Opilex 32, rue Victor Lagrange 69007 Lyon / FR | [N/P] |
| Former [2014/03] | Guérin, Jean-Philippe, et al Opilex 310 avenue Berthelot 69008 Lyon / FR | Application number, filing date | 13175435.0 | 05.07.2013 | [2014/03] | Priority number, date | FR20120056802 | 13.07.2012 Original published format: FR 1256802 | [2014/03] | Filing language | FR | Procedural language | FR | Publication | Type: | A1 Application with search report | No.: | EP2685500 | Date: | 15.01.2014 | Language: | FR | [2014/03] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 25.07.2013 | Classification | IPC: | H01L27/12, H01L27/02, H01L27/06 | [2014/03] | CPC: |
H01L27/0262 (EP,US);
H01L27/1203 (US);
H01L27/0296 (US);
H01L27/1207 (EP,US);
H01L27/0688 (EP,US)
| Designated contracting states | AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LI, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR [2014/03] | Extension states | BA | Not yet paid | ME | Not yet paid | Title | German: | Integrierte Schaltung auf SOI mit einem Thyristor (SCR) zum Schutz vor elektrostatischen Entladungen | [2014/03] | English: | Integrated circuit on SOI comprising a thyristor (SCR) protecting against electrostatic discharges | [2014/03] | French: | Circuit intégré sur soi comprenant un thyristor (scr) de protection contre des décharges électrostatiques | [2014/45] |
| Former [2014/03] | Circuit integré sur soi comprenant un thyristor (scr) de protection contre des décharges électrostatiques | Examination procedure | 11.07.2014 | Examination requested [2014/34] | 13.10.2014 | Communication of intention to grant the patent | 24.02.2015 | Application deemed to be withdrawn, date of legal effect [2015/34] | 01.04.2015 | Despatch of communication that the application is deemed to be withdrawn, reason: fee for grant / fee for printing not paid in time [2015/34] | Divisional application(s) | The date of the Examining Division's first communication in respect of the earliest application for which a communication has been issued is 13.10.2014 |
| Opt-out from the exclusive Tooltip competence of the Unified Patent Court | See the Register of the Unified Patent Court for opt-out data | ||
| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [A]US2006027877 (INABA SATOSHI [JP]) [A] 1-14 * paragraphs [0043] , [0044] , [0046] , [0047] , [0054] * * figures 2,3,5 *; | [A]US2007063284 (KAWAHARA TAKAYUKI [JP], et al) [A] 1-14 * abstract * * figures 4B,12B * * paragraphs [0072] , [0083] *; | [A]US2009026542 (WAHL UWE [DE]) [A] 1-14 * abstract * * paragraphs [0060] - [0076] * * figures 2A-2E *; | [A]WO2010112585 (COMMISSARIAT ENERGIE ATOMIQUE [FR], et al) [A] 1-14* abstract *; | [AD] - JEAN-PHILIPPE NOEL ET AL, "Multi- $V_{T}$ UTBB FDSOI Device Architectures for Low-Power CMOS Circuit", IEEE TRANSACTIONS ON ELECTRON DEVICES, IEEE SERVICE CENTER, PISACATAWAY, NJ, US, (20110801), vol. 58, no. 8, doi:10.1109/TED.2011.2155658, ISSN 0018-9383, pages 2473 - 2482, XP011336322 [AD] 1-14 * the whole document * DOI: http://dx.doi.org/10.1109/TED.2011.2155658 | by applicant | - "Multi-VT UTBB FDSOI Device Architectures for Low- Power CMOS Circuit", IEEE TRANSACTIONS ON ELECTRON DEVICES, IEEE SERVICE CENTER, (20110801), vol. 58, no. CS, pages 2473 - 2482 |